X-ray radiation is widely used for digital imaging in medical, industrial, scientific, cultural heritage, and security applications. The advent of highly integrated electronics has enabled the development of digital imaging devices that combine high-density pixel matrices with in-pixel intelligence, enabling precise energy discrimination during image acquisition. In X-ray imaging, energy discrimination not only enhances image quality by rejecting background noise but also supports advanced measurement techniques, such as those used to identify specific materials within a sample (Taguchi, 2013; Stein et al., 2023; Tortora et al., 2022). Achieving superior image quality requires balancing different detector capabilities, in particular spatial and energy resolution. Improvements in the spatial resolution of the detector, typically achieved by designing ever smaller pixels, are counterbalanced by charge-sharing issues that affect the performance of the detector for pixel size below 100 μ m (Mathieson et al., 2002). Since their first implementations in the late 1970s, Hybrid-Pixel-Detectors (HPDs) based on VLSI readout ASICs have attracted the interest of researchers thanks to Moore’s Law-driven increases in pixel capacity. A continuous increase in the number of functions integrated in the pixel cell was possible and particle sensing techniques gained a strong advantage in terms of signal-to-noise ratio, mainly due to the reduced capacitance at the front-end input node. This promising scenario motivated researchers to strive for detectors with higher spatial resolution and sensitivity. Significant efforts have led to the development of several sensor modules, some of which exhibit exceptional performance metrics. In particular, sensor modules such as the Medipix/Timepix (CERN, Llopart et al. (2022); Sriskaran et al. (2024)), EIGER (Dectris Inc., Radicci et al. (2012)), and PIXIE (Pixirad Imaging Counters Srl, INFN Spin-off, Bellazzini et al. (2013); Bellazzini et al. (2015)) have demonstrated outstanding capabilities. However, their energy and spatial resolution still limit the sensitivity of many of the measurement setups or equipment in which they are involved. In these devices, the output signal of the pixel amplifier is continuously compared with a global threshold, and the content of a dedicated counter is incremented whenever the signal crosses it, or alternatively, the amplitude of the signal is sampled by means of time-over-threshold techniques. In these architectures, imaging performance is inherently limited by electronic noise, threshold uniformity, and charge sharing issues. While these challenges can be mitigated to some extent by design-for-matching techniques and intelligent in-pixel charge summing schemes (Bellazzini et al., 2015; Sriskaran et al., 2024), they cannot be completely eliminated. For small-pixel devices, charge sharing remains the primary limiting factor for both energy and spatial resolution (Ballabriga et al., 2020). The ASIX (Analog Spectral Imager for X-rays) R&D project is focused on developing a small-scale ( ∼ 5 × 5    m m 2 ) technology demonstrator aimed at overcoming fundamental limitations in HPDs used for X-ray spectral imaging. ASIX will incorporate 50 μ m pixels in a hexagonal array with single-photon, ultra-low-noise analog readout ( < 30 e − ENC), capable of precisely sampling the full charge distribution generated by the X-ray photon absorption, thus enabling high spatial (10 μ m) and energy resolution (350 eV FWHM at 8 keV) in a single measurement. Thanks to its targeted performance, ASIX has the potential to improve sensitivity in applications requiring precise determination of both the energy and position of detected X-ray photons. The following sections outline our approach and report initial results from the ASIX Minimum Viable Product (ASIX-MVP), a CNTT-funded project to develop an intermediate HPD prototype designed to validate preliminary models predicting the resolution performance envisioned for the ASIX demonstrator.

In pixel detectors, charge sharing occurs when an incoming X-ray photon deposits charge that spreads across multiple adjacent pixels, making it difficult to assign the event to a single pixel. Traditionally, in photon counting detectors, charge sharing is considered a drawback because it degrades both energy resolution and positional accuracy by splitting charge among neighboring pixels (Delogu et al., 2023). In systems with analog readout, charge sharing is a key factor enabling sub-pixel resolution imaging, delivering higher precision as the average size of the charge cluster increases. Unfortunately, while the sensor’s spatial resolution benefits from charge sharing, the energy resolution does not. Indeed, electronic noise comes into play, limiting the best achievable energy resolution. As the average cluster size increases, so does the uncertainty in the sum of the individual pixel signals (Dinapoli et al. (2014); Cartier et al. (2016)). It must be noted that it is always possible to filter data to limit the average cluster size, thus improving the final energy resolution. However, this filtering negatively affects the spatial resolution and the sensor’s data production rate. As a matter of fact, pixel detector systems do not perform equally well in all this metrics, and a trade-off must be set by tuning the sensor specifications in terms of pixel size, electronic noise, and sensor thickness. In our design we combine a fine-pitch 50   μ m pixel and an ultra-low-noise, fully analog readout with a self-triggering logic capable of identifying the pixel with the maximum charge and selecting it for readout along with its six neighbors (hexagonal matrix). With such detailed information available offline for every single photon, we shape the charge cluster by comparing the seven-pixel charge content against a digital threshold set at the pixel’s noise level, after which we reconstruct:

• the photon absorption point, estimated as the centroid (center of gravity) of the charge distribution;

Given the ASIX’s baseline specifications, namely, the 50   μ m pixel size and 300   μ m thick silicon sensor, this approach is expected to deliver simultaneous moderate sub-pixel resolution ( 10 μ m) and energy resolved ( 350   e V , FWHM at 8 keV) X-ray imaging. A drawback of this charge-cluster reconstruction is the increased processing time per event. However, ASIX will counteract this side-effect by employing a highly parallelized architecture, distributing workload across multiple Analog-to-Digital-Converters (ADCs) integrated on chip with a density of ∼ 1 0 3 A D C s / c m 2 . This will allow simultaneous digitization of multiple clusters. The 65-nm CMOS technology, selected for the ASIX demonstrator, enables the implementation of a highly packed digital electronics in the output data path, leading to high-speed serialization and supporting a rate capability of up to 1 0 8   p h / s / c m 2 .

INFN and Fondazione Bruno Kessler, supported the ASIX-MVP project, which aimed to develop a Minimum-Viable-Product (MVP) for the ASIX demonstrator. The goal was to demonstrate the effectiveness of our preliminary models in predicting the performance of our sensor given the configuration in terms of pixel size, sensor material and thickness, and readout noise. The MVP builds upon XPOL-III, a large scale ( ∼ 2   c m 2 ) readout ASIC, which was readily available at INFN together with a companion FPGA based Data Acquistion system (DAQ). XPOL-III was originally developed to be integrated at the core of space-borne X-ray telescopes dedicated to polarimetry measurement in the 2 keV–8 keV energy range (Minuti et al., 2023). It features a 304 × 352 pixel hexagonal matrix, comprising over a 100 k channels each occupying a 50 × 43   μ m 2 area. Pixels include a contact pad on its top metal layer, which connects to a low-noise spectroscopic chain consisting of a Charge-Sensing Amplifier (CSA) with 30   k e − input linear range, a shaper with 1   μ s peaking time, and a self-triggering peak detector circuit. When a charge is detected at the CSA input pad, XPOL-III isolates a rectangular Region of Interest (ROI), selecting for readout the pixels that detected a significant charge ( ∼ 300   e − ) plus a margin (configurable in the 1 to 16 pixels range). During the readout sequence, which is controlled by the DAQ electronics, the amplifier output of the pixels belonging the ROI are sequentially connected to an analog output pad for off-chip analog-to-digital conversion, thus enabling precise single-photon processing. Moreover, once the original signal has been acquired, the peak detectors are cleared and the same ROI is readout several times (up to 4, configurable) for pedestal evaluation. The “pedestals” ROIs are averaged and subtracted from the “signal” ROI onboard the FPGA on an event-by-event basis. This enables for continuos accurate compensation of the pixel output baseline drift across temperature and sensor bias variations. In our system, a personal computer, running a dedicated application software, receives ROIs containing the photon data one by one from the DAQ. Typically, each ROI contains data related to one single photon. For each of them, we extract the exact charge distribution by performing basic zero suppression, comparing the pixel signal versus a threshold which is an input parameter of our algorithm. We then estimate the cluster size, i.e., how many pixels detected a significant charge, compute the photon absorption point and its energy. In our analysis, we have set this clustering threshold down to a 1-sigma noise level and configured the online pedestal subtraction logic in the FPGA to average four pedestal ROIs. The rate capability of this readout ( 1 0 3   p h / s / c m 2 ) , achieved with a minimal segmentation ( ∼ 0.5   A D C s / c m 2 ) , poses a significant limitation for the use cases targeted by ASIX. However, its pixel geometry and readout principle, namely, 50 μ m hexagonal arrangement and analog readout, are fully compatible with ASIX. Combined with its good noise performance and response uniformity, these features made XPOL-III a suitable candidate for the MVP development.

Although our baseline sensor is a ∼ 300   μ m silicon, coupling the ASIX readout to sensors made of different materials and thicknesses would broaden the range of potential applications for the new device. With this in mind, ASIX-MVP was designed to exploit the versatility that is typical of hybrid pixel detectors.

In December 2024, we delivered two HPD variants:

• a 750   μ m thick Cadmium-Telluride (CdTe) Schottky-type sensor with 100   μ m pixels

Both coupled to the same XPOL-III readout ASIC.

In the following subsections, we synthesize the ASIX MVPs basic properties evaluation process and its outcomes. The basic characteristics of the Si and CdTe hybrids are summarized in Table 1.

Thanks to the fine pitch pixels, fully-analog event-driven readout, and targeted energy and spatial resolution, the ASIX’s expected performance, combined with the versatility of hybrid pixel detectors, would offer several advantages over similar state-of-the-art detectors, opening the door to a wide range of applications that benefit from high-resolution effective single-photon processing. These applications can be broadly grouped into three main areas which we list in the following sub-sections.

With the measured 7   μ m spatial resolution and energy resolution (660 eV FWHM at 9.7 keV) limited by electronic noise in the 300   μ m thick silicon sensor, the MVP data demonstrate the feasibility of achieving simultaneous high spatial and energy resolution using a small-pixel hybrid pixel detector, paving the way for the next phase of ASIX development. To fully qualify the technology, a new hybrid must be realized, one that integrates a redesigned readout ASIC tailored to the ASIX architecture. The upcoming ASIC will be engineered to meet stringent noise performance requirements ( < 30   e − , ENC) while introducing a novel, parallel readout architecture based on multiple on-chip Analog-to-Digital Converters. This enhancement will enable efficient cluster-based readout at high event rates (up to 1 0 8   p h / s / c m 2 target).

In the long term, ASIX is envisioned as a scalable building block for large-area sensor matrices with minimal inactive regions. Its modular architecture ensures that expanded arrays can maintain high-resolution performance with manageable interconnect complexity, supporting deployment in advanced imaging systems across various domains. Over the next 2 years (2025–2026), the ASIX team will focus on developing this next-generation readout ASIC. In parallel, we will fabricate an edgeless silicon sensor using an innovative construction process built on top of that proposed by Koybasi et al. (2020), aimed at preserving wafer integrity without the use of a support wafer. These advancements will be key to transitioning ASIX from a promising demonstrator to a mature, deployable platform for high-performance X-ray spectral imaging. The ASIX project offers a novel approach to overcoming the long-standing trade-off between spatial and energy resolution in hybrid pixel detectors. By leveraging fine-pitch pixels, ultra-low-noise analog readout, and cluster-based reconstruction, ASIX will turn charge-sharing into an asset, enabling sub-pixel localization along with spectral fidelity. With its potential to deliver high-resolution, energy-resolved imaging, ASIX is well positioned to impact a wide range of applications, from materials analysis and biomedical imaging to astrophysics and remote sensing.