The gold-coated part of the FO-SPR gate electrode is electrically contacted with the SPR active zone and immersed into the electrolyte solution on the top of the FET substrate, as illustrated in Figure 1A. A gate voltage is applied, and the resulting drain-source current modulation can be described in the linear region of EG-FET devices, V D S ≪ V G − V T , as: I D S = W L C i μ V G − V T V D S , (1) where W is the channel width, L the channel length, C i the insulating layer capacitance, μ the charge mobility of the semiconductor, V G the applied gate voltage, V T the threshold voltage, and V D S the applied drain-source voltage. Simultaneously, the FO-SPR gate coated with a thin gold film is connected to an optical Y-splitter. It is used to couple polychromatic light to the FO tip which is back reflected and launched to a spectrometer. The acquired optical spectrum exhibits a resonant dip at a wavelength where SPR occurs due to the excitation of surface plasmons (SP) propagating at the gate-electrolyte interface. This SPR wavelength shifts when changing the refractive index of the dielectric medium adjacent to the metal surface. Figure 1A shows a schematic representation of the utilized dual-mode setup of FO-SPR and EG-FET. As previously reported, applying a gate potential alters the optical properties of this metal-electrolyte interface and, therefore, influences the optical signal obtained from the FO-SPR gate [11]. As shown in Figure 1B, applying a gate potential yields an offset of the resonance wavelength. The direction and strength of the resulting offset depend on the frequency and magnitude of the applied gate potential modulation. This offset upon potential change is mainly dominated by the formation of ionic complexes on the metal surface [14]. Furthermore, applying an electrochemical potential on as-prepared FO-SPR gate electrodes leads to an optical signal drift and irreversible blue-shift of the resonance wavelength (Figure 1B), adding extra constraints to a dual-mode application of these FO-SPR gate electrodes. Overall, a higher magnitude and/or longer periods of the applied potential lead to more pronounced blue-shifts. It has been shown that physically deposited metal films undergo a recrystallization upon application of an electrochemical potential, with no charge transfer reactions involved [13]. Additionally, electrochemical treatments can lead to surface reconstitution and influence crystallinity [22, 23], used for example, as preconditioning to ensure a reproducible formation of high-quality SAM on gold [24]. It is worth noting that all other possible electrochemical processes, such as the adsorption of ions (e.g., Cl⁻) from the electrolyte would lead to the formation of an optically dense layer and, therefore, a red-shift of the resonance wavelength is expected to occur [13]. Thus, our observations, in combination with previously reported studies, suggest a surface morphology change and recrystallization of the gold grains of as-sputtered FO-SPR gates upon prolonged V _G application. In order to increase the optical signal stability when such tips are used in their dual-mode purpose, different FO-SPR gate modifications were investigated (Figure 1C). On the one hand, such potential-induced effects on the surface morphology should be minimized if the Au surface is passivated, e.g., by functionalization with a SAM typically used in biosensing assays. Alternatively, it has been reported that mild annealing can lead to structural changes in thin gold films [16–18, 25]. By preconditioning the as-sputtered FO-SPR gates with a thermal treatment, the impact of the subsequently applied electrochemical potential on the surface morphology should be minimized.

As-sputtered FO-SPR gates were therefore thermally annealed at 130, 180, and 230°C for 2, 7, and 12 h. This range of investigated temperatures has been previously reported to induce structural changes in the thin gold layer without damaging the other layers of the fiber optic probe, leaving the possibility for optical sensing intact [18]. Figure 2A shows the SEM images of the FO-SPR gate surface after sputtering and after annealing at 180°C for 7 h, respectively. After sputtering, the gold surface shows a pronounced granular morphology. The thermal treatment leads to a coalescence of the Au grains into larger domains. This agrees with a previously reported study that shows that this temperature and time range does not lead to a significant change of the surface roughness but rather a strong increase of the average grain size lateral dimension [18]. Similar effects on increasing the grains lateral dimension upon annealing have been reported using scanning tunneling microscopy (STM) [15]. The observed grain growth depends on the strength and time duration of the applied temperature increase. At elevated temperatures, thin, continuous gold films are known to form island-like structures with voids [26]. It has been reported that surface diffusion dominates the thermal annealing process of thin gold films with a relatively low thermal activation energy [15, 25, 27, 28]. As a result, the optical signal shows a significant blue-shift of Δλ _SPR = −52.3 ± 1.2 nm (Figure 2B and Supplementary Figure S1) and, furthermore, a significant reduction in full width half maximum (FWHM) of the plasmonic dip (Supplementary Figure S1) of ΔFWHM = −25.7 ± 4.9 nm, compared to the signal of the FO-SPR gate after sputtering without thermal treatment (denoted as “RT”). This further indicates that the dominating effect is not an increase in surface roughness since an increased surface roughness would lead to a broadening of the SPR dip in the reflectivity spectrum [29, 30] due to the more pronounced damping of surface plasmons [29, 31]. More importantly, the FWHM impacts the optical signal’s spectral resolution and is, therefore, an important measure of the quality of the FO-SPR gate. Mild thermal annealing not just shifts the resonance dip to lower wavelengths which opens a larger measurement window but also leads to a narrowing of the resonance dip, improving the overall resolution.

It has to be noted that the annealing step also impacts the bulk refractive index sensitivity S _B of the FO-SPR gate. In a previously reported study a significant increase in bulk sensitivity was observed after annealing the FO tips in the investigated temperature range [18]. The authors of this study associate this sensitivity improvement with an increased plasmonic behavior at the semi-continuous domains created due to the thermal treatment. We have not observed such a sensitivity increase but rather a decrease, associated with the spectral blue-shift of the resonance wavelength. It has been shown with ellipsometry that various annealing temperatures below 300°C cause changes of the (effective) optical constants of gold films deposited on silicon substrates [32]. This results in a change of the resonance condition and a blue-shift of the resonance wavelength. The determined S _B after the thermal annealing is in accordance with the analytical model based on Fresnel multilayer reflectivity that suggests S _B decreasing when decreasing the SPR wavelength (Supplementary Figure S2). However, even the reduced S _B provides a high enough sensitivity for the intended application of the FO-SPR gate for multimodal biosensing and is not the only parameter to consider when discussing the overall quality of the optical signal. As shown in Supplementary Figure S3, the spectral quality (Q-factor) as well as the refractive index resolution is improved for all annealing conditions compared to as-sputtered FO-SPR gate electrodes.

To evaluate the impact of the surface morphology change due to thermal annealing on the electronic sensing, such FO-SPR gates were connected in an EG-FET configuration using FETs with reduced graphene oxide (rGO) as channel material. The FO-SPR gates were then immersed in the reaction chamber containing 100 mM KCl as electrolyte and the FET substrate at the bottom (Figure 1A). I _DS V _G transfer curves for different annealing conditions were recorded, with a V _DS of 50 mV, using the same FET substrate immersed in the electrolyte and exchanging the FO-SPR gate consecutively. For rGO, typical ambipolar transfer curves were obtained, with the minimum being denoted as Dirac point V _i. The recorded curves have been aligned by subtracting the minimum current at the Dirac point I _DS(V _i), therefore plotting the drain-source current shift ΔI _DS = I _DS(V _G)—I _DS(V _i), to eliminate a possible signal drift. As previously reported, the electronic signal obtained from this FO-SPR gate electrodes strongly depends on the FO-SPR gate surface area A _g [11]. The obtained drain-source current shifts were normalized by the geometrical surface area A _g for the given FO-SPR gate (average A _g: 29 ± 2 mm²) to avoid the influence thereof due to differences in length for the differently annealed fiber tips. Obtained results for the transfer curve and the leakage current I _G are shown in Figure 2C. The surface morphology change of the FO-SPR gate causes a significant impact on the gate-electrolyte interfacial capacitance and therefore affects the slope of the hole and electron accumulation branch, respectively.

The microscopic changes of the FO-SPR gate surface affect the electronically active surface area A and, thus, the formation of the electrical double layer. The associated change in capacitance can be related to a change in surface area by the well-known capacitor equation C = ε 0 ε r A / d , were ε 0 is the vacuum permittivity, ε r relative permittivity, d is the distance. This agrees with previously reported studies discussing the effect of rough electrodes on the capacitance of thin films [20, 33, 34]. Using a previously reported method [11], we determined the total interfacial capacitance for the EG-FET using the differently annealed FO-SPR gates and the change thereof with respect to the untreated FO-SPR gate (“RT”) is shown in Figure 2D. A decrease in total interfacial capacitance was observed for different annealing conditions, resulting in a lower I _DS at a given gate potential according to Eq. 1. This could be explained by a smoothening of the surface due to the coalescence of the Au grains into larger domains, leading to levelling of surface height fluctuations [15, 28]. However, it is difficult to distinguish between crystal grain size or other possible effects contributing to the electronic response, such as macroscopic and microscopic surface roughness, holes in the film due to the formation of semi-continuous films upon thermal treatment, or impurities. It is worth noting that the decrease in capacitance and associated, shallower slopes of the transfer curve result in a reduction of the maximum transconductance g _m, defined as the ratio of I _DS at V _G = −0.5 V and I _DS(V _i) (Figure 2D). The transconductance is tightly related to the sensitivity of the electronic response. A high maximum transconductance implies a high modulation efficiency, resulting in a stronger signal amplification. The observed reduction of the maximum transconductance therefore represents a drawback for electronic sensing since it leads to a less pronounced current modulation and lower electronic performance.

As previously described [11], by recording the leakage current at different scan rates while sweeping V _G, it is possible to deconvolute Coulombic and Faradaic contributions. Untreated FO-SPR gate electrodes show an increase in Faradaic currents as a result of increasing the geometrical FO-SPR gate area by using a larger fiber core diameter [11]. Potential Faradaic side reactions occurring during EG-FET operation might form reactive side products that could harm the devices’ biological functionalization or lead to accelerated degradation [35]. Interestingly, upon thermal annealing, the Faradaic contribution can be reduced, possibly overcoming this drawback to some extent (Figure 2E). A table summarizing the optical and electronic performance factors obtained after the different thermal treatments can be found in the SI (Supplementary Table S1).

Alternatively, the FO-SPR gate can be passivated using a standard carboxy-terminated thiol SAM. It has been reported that applying a thiol SAM on the gate in a top-gated EG-FET configuration leads to a decrease in capacitance [36]. This results in shallower slopes and reduced transconductance for SAM-coated FO-SPR gates (data not shown). However, the terminal end groups of the SAM molecules provide possible anchor points for surface functionalization typically used in bioassays. Similar to the shallower transfer curves of thermally annealed FO-SPR gates, the electronic performance is still deemed to be sufficient for sensing applications. Moreover, as expected, the gate surface passivation with a SAM reduces the Faradaic contributions to a minimum (Figure 2E).

To investigate the possible effect on optical signal stabilization, FO-SPR gate electrodes were connected optically and electronically with and without annealing. The optical signal was recorded by tracking the resonance wavelength λ _SPR over time and a gate potential of V _G = −500 mV was applied in pulses of 30 s. Pulses were applied by switching V _G ON and OFF (GND) and the drain-source current was recorded at a constant drain-source voltage for a period of 1 h. The simultaneously obtained optical and electronic signals are shown in Figures 3A, B. As can be seen in these data the potential cycles significantly impact the optical signal and a strong blue-shift of the SPR wavelength is observed for as-prepared FO-SPR gate electrodes over the period of 1 h. After the potential cycling is terminated, the resonance wavelength stays shifted, illustrating the irreversibility of this effect. A mild thermal treatment of 130°C for 2 h does not lead to a significant improvement. In both cases, an irreversible blue-shift of approximately −3 nm was measured (Supplementary Figure S4C). However, all other thermal treatments led to superior optical signal stability, showing no significant signal drift and irreversible blue-shift of the resonance wavelength (Figure 3A). We assume that the thermal stress saturates the surface morphology changes that otherwise would be gradually imposed by applying an electrochemical potential. Interestingly, the current signal also shows improved stability compared to the untreated FO-SPR gate electrode (Figure 3B). Especially in the first 20 min of applying V_G cycles, a significant drift of the ON current was observed. In contrast, for a FO-SPR gate exposed to 180°C for 2 h, the ON current levels off and a significant variation is observed only in the first 3 cycles. A pertinent attribute of the transistor is the I _ON/I _OFF ratio. As illustrated in Figure 3B, without thermal annealing, a significant variation of the I _ON/I _OFF ratio was obtained whereas with a thermally treated FO-SPR gate a constant I _ON/I _OFF ratio was observed. This is expected as the same surface morphology changes that affect the optical signal also influence the gate-electrolyte interfacial capacitance, as discussed above. The morphological changes induced by the applied gate potential lead to a decrease of the interfacial capacitance, resulting in lower I _ON over time. The prior annealing of the FO-SPR gate saturates such changes, as shown in Figure 2D, ensuring a constant I _ON/I _OFF ratio over time.

Counterions from the electrolyte, e.g., halides, can strongly bind to the surface of the gold electrode [37] and experience high local field strengths upon applying an electrochemical potential [38, 39]. Previous studies suggest that the potential-induced grain growth is related to a gold surface reconstruction induced by counterion adsorption [13]. It has been shown that double-layer charging can cause morphology changes and affects the crystallinity of small gold rods [40]. Therefore, the grain boundaries are expected to act as electrochemical cells, at which atomic reconstruction occurs spontaneously due to reversible interactions with counterions, promoted by the applied potential [13]. The thermal treatment implies a tension on the thin Au layer of the FO-SPR gate and induces grain growth leading to a reduction of grain boundaries compared to the granular surface morphology obtained after sputtering. We hypothesize that this accounts for preventing a further influence of an applied electrochemical potential, leading to the observed optical and electronic signal stabilization. Supplementary Figure S4 shows the obtained spectra before and after 1 h of V _G cycles for an untreated and a thermally annealed (180°C/7 h) FO-SPR gate electrode. It is worth noting that the thermally treated FO-SPR gate shows no significant change in the obtained spectrum after the potential cycles. Untreated FO-SPR gates, on the other hand, show a significant blue-shift as already seen for the real-time optical signal. Furthermore, a significant increase in FWHM was also observed (Supplementary Figure S4D). This could be associated with plasmonic damping due to potential-induced changes of the surface morphology. Thermal annealing not just prevents a spectral blue-shift but also the spectral broadening of the resonance dip is eliminated, ensuring a constant optical resolution throughout a dual-mode assay.

High signal stability is of great importance for the real-time dual-mode operation of the FO-SPR/FET platform. In this mode of operation, a constant V _G is applied to the FO-SPR gate. As for pulsed V _G application, a constant V _G of −500 mV also results in a significant signal drift for both the optical and the electronic signal of untreated FO-SPR gate electrodes (Figures 3C, D). This must be carefully considered and corrected when performing adsorption processes on the FO-SPR gate gold surface. As shown in Figure 3C, thermal annealing of the FO-SPR gate leads to superior optical signal stability during V _G application. Upon applying a gate voltage, an abrupt decrease of the resonance wavelength is observed. As previously reported, this offset is reversible and is linearly dependent on the applied gate voltage [11]. Only a minor offset of the resonance wavelength of approximately −0.4 nm was observed, possibly due to the change of the equilibrium for ionic complex formation on the surface [14]. For an as-prepared FO-SPR gate this is superimposed with an irreversible blue-shift and therefore a continuous decrease of the resonance wavelength. Thermal annealing prevents the irreversible blue-shift and thus ensures a constant offset of the resonance wavelength upon applying a gate voltage. This is an important characteristic when the FO-SPR gate is operated in its dual-mode purpose. More importantly, also superior stability of the electronic signal was observed due to the thermal pretreatment of the FO-SPR gates (Figure 3D). The measured drain-source current stabilizes within the first 5 min and stays constant, whereas untreated FO-SPR gates showed a continuous decrease in drain-source current, with drift saturation after approximately 20 min. Considering an initial stabilization period of 10 min, an optical signal drift (Δλ _SPR/S _B)/t, of −0.019 mRIU/min and an electronic signal drift (ΔI _DS/I _DS (t = 0))/t, of −0.3%/min remains for an as-sputtered FO-SPR gate, evaluated at V _G = −500 mV. Thermal exposure of the FO-SPR gate to 180°C for 7 h prior to the measurement yields an improvement of the signal drift by over an order of magnitude, namely, to −0.001 mRIU/min and −0.01%/min for the optical and electronic signal, respectively. The optical signal drift upon prolonged gate-voltage application can be attributed to surface recrystallization of the Au film [13]. The propagation constant of the surface plasmon at a metal-dielectric interface is tightly related to the optical constant of the metal film [1]. Thus, surface morphology changes alter the resonance condition and lead to a shift of the resonance wavelength. The electronic signal on the other hand is tightly related to the interfacial capacitance (Eq. 1). The surface morphology changes induced by the prolonged application of the gate-voltage affect the interfacial area and therefore its capacitance which results in a change of the measured drain-source current. Thermal treatment of the as-sputtered Au film saturates such surface morphology changes and results in Au films that are less affected by the applied gate voltage. Thermal annealing therefore leads simultaneously to superior optical and electronic signal stability, providing an immediate stable readout for the operation of FO-SPR gates in real-time without potential-induced changes of the metal-electrolyte interface and concomitant changes of the SPR and FET characteristics. Alternatively, a similar optical and electronic signal stabilization was achieved by passivating the FO-SPR gate surface with a thiol SAM (Figures 3C, D). Correspondingly, improved current stability over time was observed for FO-SPR gate electrodes coated with a fully swelled antifouling polymer brush biointerface, allowing the application of this platform in complex liquid samples [41].

The long-term stability of the fabricated FO-SPR gate is of high importance since it is a key for developing new applications of the FO-SPR/FET platform. Therefore, the FO-SPR gates stored under argon were re-evaluated after 1 year of storage. Simultaneously obtained optical and electronic signals upon application of a constant V _G = −500 mV for 20 min are shown in Figure 4. As can be seen in the case of thermal treatment at 180°C for 7 h, the thermal exposure of the FO-SPR gate ensures superior signal stabilization even after 1 year of storage. Untreated FO-SPR gates show a less pronounced but still significant signal drift, with a faster stabilization period, after long-term storage compared to the measurement right after fabrication. This is expected for a temperature-induced surface morphology change with a slower kinetic when stored at room temperature. It has been known that for metal films, e.g., with electroplated copper, a spontaneous “self-annealing” can occur over long periods [42–44]. This illustrates the change of the signal characteristics when such probes are applied in timely separated measurements. Therefore, it is crucial for obtaining comparable results and consistent performance when using such FO-SPR gates that the surface is either immediately passivated with a thiol SAM or thermally treated before storage. However, thiol SAM-coated FO-SPR gates might be used for a short time since during long-term storage a degradation of the thiol SAM molecules affecting the thiol SAM quality and structure is expected due to oxidation of the gold-thiolate bond under ambient conditions [45]. FO-SPR gates after thermal exposure would allow long-term storage with possible pre-cleaning of the surface prior to usage, e.g., via UV/ozone or cyclic voltammetry. Therefore, thermal annealing provides more robust FO-SPR gate electrodes and leads to superior optical and electronic signal stability for applying the FO-SPR/FET platform in real-time measurements.