Silicon pixel detectors have been developed in high-energy physics applications to provide precise position measurements thanks to their compactness and high spatial granularity. Recent developments have been focused on sub-100 ps timing measurements of optical photons and direct detection of charged particles.

When a particle passes through the detector, electron-hole pairs are generated. When these charges move in the depletion region, an induced current pulse is registered on one electrode. According to the Schockley-Ramo theorem [1, 2], this current is proportional to the free charge Q, to the speed of the charge carriers v, and to the weighting field, which can be expressed, to a first approximation, as 1 d , where d is the thickness of the depletion region. Hence, we can calculate the induced current as: i = k Q v 1 d , (1) where k is a proportionality factor. The signal ends when all charges have been collected. Moreover, in case of a minimum ionizing particle (MIP) crossing a thin device, the charge Q is proportional to d. We thus have: i = k N d v 1 d = k N v , (2) where N is the number of electron-hole pairs generated per unit length. This result shows that the initial value of the induced current is constant and does not depend on the thickness of the depletion region. When reading out this current signal on a load, behaving like an ideal transimpedance amplifier, we observe a sharp voltage pulse. The time-of-arrival of the charge is usually determined by comparing the voltage pulse with a threshold. The uncertainty of the voltage pulse σ _V is expressed as: σ V = σ t d V d t , (3) where σ _t is the timing jitter of the voltage pulse. By inverting Eq. 3, we find that: σ t = σ V d V d t . (4)

Equation 4 shows that the signal fluctuation (σ _V ) should be reduced to achieve a better timing jitter σ _t and the slew rate d V d t should be maximized. In case of a sensor with an internal finite gain G [3–5], the slew rate is proportional to G d . This analysis, where low gain avalanche diode (LGAD) concept is introduced, suggests that thin sensors with large internal gain will, in principle, result in a better timing jitter. As the LGAD signal needs amplification, the detector capacitance becomes crucial for the timing jitter. As reported in [6], a timing resolution of 16 ps has been achieved with a 45 μm thick and 1.7 mm² area LGAD. There is, however, another effect that can significantly affect the pulse shape while detecting MIPs: the charge collection noise. This phenomenon is caused by the variability of the profile of the deposited charge. As shown in [7], this effect introduces a timing jitter that is non-negligible at the 10 ps scale, and which increases with the detector thickness [8]. Various solutions have been proposed to reduce the contribution of this additional source of timing jitter, such as the detectors reported in [5, 9, 10].

All the effects mentioned above call for extremely high intrinsic gain and slew rate together with thin structures. Thus, Geiger-mode silicon APDs (i.e., devices biased above breakdown), also known as single-photon avalanche diodes (SPADs), could represent promising candidates for substantial timing jitter reduction [11]. In SPADs, unlike APDs, the avalanche is a self-sustaining process, and the timing jitter contributions are more related to the avalanche growth dynamics. In particular, the timing jitter improves, decreasing the avalanche current value needed by the frontend electronics to detect a pulse [12]. A comprehensive theoretical study of timing performance in SPADs when used in MIP detection is presented in [13]. First examples of such systems, detailed in [14–16], were following the concept proposed by [17].

Although these potential advantages are promising, some problems usually affect Geiger-mode devices in the framework of MIP detection. Indeed, typical SPADs have a long dead time if no properly designed active quenching and recharge techniques are used [18]. Another issue is the presence of noise in the form of spurious pulses even in the dark. This noise, known as dark count rate (DCR), could limit the suitability of SPADs for the target application because of significant degradation of the measurement signal-to-noise ratio (SNR). However, as shown by [19, 20], DCR can be drastically reduced by detecting MIPs with two SPADs operated in coincidence. Building on these elements, we present MIP time-of-flight (ToF) measurements resulting in unprecedented timing precision.

The detector system used in this work relies on the SPAD-based sensor presented in [21]. This device’s cross-section is based on a substrate-isolated type, where a p-well (PW) layer forms the anode of the SPAD and a buried n-well (BNW) layer creates the cathode contact. The latter is connected to the high voltage through a deep-n-well (DNW). The SPAD presents a p-i-n structure [21]. Figure 1A shows the cross-section of the SPAD, while Figure 1B shows a micrograph of the sensor used in this study. The guard ring has a virtual design and employs a low doping p-Epi region located between the PW and the DNW contact to smooth the doping transition and lower the electric field. Thus, a p-Epi layer between anode and cathode allows a relatively extended and uniform high-field region (Figure 2A).

The sensor integrates four independent SPAD pixels with a diameter of 25 μm. A dedicated on-chip front-end circuitry, shown in Figure 3, is implemented in close proximity to each SPAD. In the SPAD front-end circuit (see Figure 3) the cascode transistor M ₁ is used as a resistive divider and voltage clamp, along with M ₂ to enable high excess bias. This comes in combination with thin-oxide MOS transistors in the remainder of the front-end to improve the timing performance. M ₂ and M ₃ form the active recharge branch, turned on by the feedback loop composed by the NOR gate, Schmitt trigger, and tunable delay element (see Figure 3 right). The circuit is designed to enable a tunable dead time, as short as 3 ns, supporting very high count rates while still maintaining very low afterpulsing [21]. Concerning the leakage current for this detector, as reported in [21], the measured value is on the order of 0.1–1 pA, which corresponds to a value of about 0.4-4 fA/μm ².

In this work, we implemented a complete and optimized system-on-board to further improve performance. The resulting system comprises a motherboard, where all needed voltage levels are derived from a single 5 V power supply. A power management unit was designed to filter most of the electronic noise and to provide low-noise and stable voltage levels to the detector and its front-end circuits. Moreover, the full integration of a system-on-board reduces the noise picked up in cables and power cords that can act as antennas. Indeed, reducing the noise in the system is essential when the target timing precision approaches 10 ps [3]. A full system control is achieved with a serial bus interface that allows the tuning of the device operating point from an host computer.

The output of the chip is connected to fast SiGe comparators (Analog Device ADCMP572) that drive 50 Ω lines (Figure 3). This solution reduces the capacitive load at the chip’s output (high impedance node) and helps propagate the signal through a high-frequency cable to the timestamping electronics. In addition, the use of these comparators makes it possible to achieve high signal slew rate (≥1.6 V/ns).