Reliability of Buried InGaAs Channel n-MOSFETs With an InP Barrier Layer and Al2O3 Dielectric Under Positive Bias Temperature Instability Stress - Li, Haiou; Qu, Kangchun; Gao, Xi; Li, Yue; Chen, Yonghe; Zhou, Zhiping; Ma, Lei; Zhang, Fabi; Zhang, Xiaowen; Fu, Tao; Liu, Xingpeng; Liu, Yingbo; et al. (Frontiers in Physics, 2020)
The positive bias temperature instability (PBTI) reliability of buried InGaAs channel n-MOSFETs with an InP barrier layer and Al2O3 gate dielectric under medium field (2.7 MV/cm) and high field (5.0 MV/cm) are investigated in this paper. The Al2O3/InP interface of the insertion of an InP barrier layer has fewer interface and border traps compared to that of the Al2O3/InGaAs interface. The subthreshold slope, transconductance, and shift of Vg are studied by using the direct-current Id-Vg measurements under the PBTI stress. The experimental results show that the degradation of positive ΔVg under the medium field stress is mainly caused by the acceptor trap, while the donor trap under the high field stress become dominant in the subthreshold region, which leads to the negative shift in Vg. The generation of acceptor trap are attributed by the InP barrier layer in the buried InGaAs channel n-MOSFETs, resulting that the part of recoverable donor trap has been neutralized under the high field stress. Compared to the surface InGaAs channel n-MOSFETs under PBTI stress, the low leakage current can be achieved in the buried InGaAs channel n-MOSFETs with an InP barrier layer.