A simple spiking neuron model, also known as an integrate-and-fire-type (IF) neuron model, is shown in Figure 1 (Maass, 1999). In this model, a neuron receives spike pulses via synapses. A spike pulse only indicates the input timing, and its pulse width and amplitude do not affect the following processing. A spike generates a temporal voltage change, which is called a post-synaptic potential (PSP), and the internal potential of the n-th neuron, V_n(t), is equal to the spatiotemporal summation of all PSPs. When V_n(t) reaches the firing threshold θ, the neuron outputs a spike, and V_n(t) then settles back to the steady state.

Based on the model proposed in Maass (1997a), a simplified weighted-sum operation model using IF neurons is proposed. The time span T_in is defined, during which only one spike is fed from each neuron, and it is assumed that a PSP generated by a spike from neuron i increases linearly with slope k_i from the timing of the spike input, t_i, as shown in Figure 1.

A required weighted-sum operation is that normalized variables x_i (0 ≤ x_i ≤ 1, i = 1, 2, ⋯ , N) are multiplied by weight coefficients a_i, and the multiplication results are summed regarding i, where N is the number of inputs. This weighted-sum operation can be performed using the rise timing of PSPs in the IF neuron model. Input spike timing t_i is determined based on x_i using the following relation:

Coefficients a_i are transformed into the PSP slopes k_i:

where λ is a positive constant. If the firing time of the neuron is defined as t_ν, we easily obtain the equation

If we define the following parameters:

we obtain

Here, we assume that all the weights in the calculation have the same sign, i.e., a_i≥0 or a_i ≤ 0 for all i. This is different from the previous similar work in which only the sum of weights is restricted to be positive for firing (Zhang et al., 2021). When all inputs are minimum (∀i x_i = 0), the left side of Equation 6 is zero. Then, the output timing t_ν is given by

On the other hand, when all inputs are maximum (∀i x_i = 1), the left side of Equation 6 is β, and the output timing t_ν is given by

The time span during which t_ν can be output is [tνmax,tνmin], and its interval is

Thus, the time span of output spikes is the same as that of input spikes, T_in.

In this model, since the normalization of the sum of a_i (β = 1) is not required [unlike in the previous work (Maass, 1997a, 1999; Tohara et al., 2016)], the calculation process becomes much simpler. When implementing the time-domain weighted-sum operation, setting the threshold potential θ properly is the key to making the operation work appropriately. As shown in Figure 1, the earliest output spike timing has to be later than the latest input spike timing T_in; that is, tνmax≥Tin. Thus,

Also, we can rewrite Equation 11 as

where ϵ≥0 is an arbitrarily small value. By substituting Equations 12, 13 into Equations 8, 9, we obtain

where ϵT_in is considered as a time slot between input and output timing spans, as shown in Figure 1, and ϵ determines the length of the slot.

We propose a time-domain weighted-sum calculation model with two spiking neurons, one for all the positive weights and the other for all the negative ones. We apply Equation 6 to each neuron, and the two results are summed as the final result of the original weighted sum. Here, we show the details of the model.

Let ai+ and ai- indicate the positive and negative weights, respectively. We define

Where N⁺ and N⁻ are the numbers of positive and negative weights, respectively:

Thus, assuming λ = 1, Equation 4 is rewritten for the positive and negative weighted-sum operations as

where θ⁺(>0), θ⁻(<0), and tν+ and tν- indicate the threshold values and output timings for the positively and negatively weighted-sum operation, respectively. We obtain

Therefore, we can obtain the original weighted-sum result:

Let us define a dummy weight a₀ as the difference between both absolute values of β^±:

If β⁺≥−β⁻, then a₀ ≤ 0 and this dummy weight is incorporated into the negative weight group, and vice versa. This dummy weight is related to a zero input, x₀ = 0, which means t₀ = T_in. By using the dummy weight, we can make the absolute values of β^± identical (β = 0), and we define

Also, according to Equations 12, 13, the absolute values of θ⁺ and θ⁻ can be the same, and θ⁺+θ⁻ = 0. Therefore, Equation 22 can be rewritten as

The typical neuron model of ANNs is shown in Figure 2a, which has N inputs x_i with weights w_i and a bias b;

where y is the output of the neuron, and f is an activation function. We can consider the bias as a weight whose input is always unity and regard the 0 index weight as the bias throughout this paper. Therefore, our time-domain weighted-sum calculation model with the dummy weight can be applied to this neuron model, as shown in Figure 2b. According to Equation 25,

Based on Equation 27, we propose another model, shown in Figure 2c, in which each synapse has two sets of inputs and weights; one is (x_i, w_i) and the other is (0, −w_i). In this model, it is not necessary to add a dummy weight because the summation of positive weights is equal to the absolute one of negative weights automatically, i.e., β=∑i=0N||wi||.

As the activation function f, we often use the rectified linear unit called “ReLU” (Nair and Hinton, 2010), which is defined as follows:

We can implement the ReLU function by comparing the output timings tν- and tν+ in the time-domain weighted-sum calculation as follows:

where, if tν->tν+, the difference between the two timing values is regarded as the output transferred to neurons in the next layer, and if tν-<tν+, we set tν- and tν+ to be identical to make the output zero because of the negative weighted-sum result. Its circuit implementation will be shown later.

In this section, we extend our time-domain neuron model shown in Figure 2c to the neural network and theoretically show the intermediate timing transfer mechanisms between layers. We first apply the procedure to a two-layer MLP, which has one hidden layer and two sets of input and weight for each neuron shown in Figure 3, as an example, and then generalize it.

In this MLP, according to Equation 27, the weighted-sum result of the j-th neuron in the hidden layer labeled as n can be

where βj(n)=∑i=0N||wij(n)||, tvj(n)- and tvj(n)+ are the timings generated at the j-th neuron in the n-th layer. The output yk(p) of the k-th neuron in the output layer labeled as p(= n+1) is

where ReLU is used as the activation function, and the bias bk(p)=w0k(p) is represented in the time-domain model by

in which tv0(n)+=Tin is paired to w0k(p), tv0(n)-=0 is paired to -w0k(p) and β0(n)=1 as there is no input to the bias.

In the MLP shown in Figure 3, we transfer the output timings tvj(n)+ and tvj(n)- generated in layer n to the neurons in layer p and perform the time-domain weighted-sum operation. The timings tvk(p)+ and tvk(p)- are assumed to be produced at the k-th neuron of layer p. We relate timing tvj(n)+ to weight wjk(p) and tvj(n)- to -wjk(p). We also assume here N = 3 and that w1k(p)≥0,w2k(p)<0,w3k(p)≥0,bk(p)≥0, and θk(p)+=-θk(p)-, where θk(p)+ and θk(p)- are the threshold values for positively and negatively weighted-sum operations, respectively. Thus, according to Equation 4, we can obtain

By adding Equation 33 to Equation 34 on the left and right sides, respectively, the following relationship is obtained:

Thus, we can obtain the following simple expression:

Therefore, we generalize the number of neurons N = 3 to N again, and replace Equation 36 with Equation 31. Then, the output yk(p) in Equation 31 can finally be

As a result, for neurons in the hidden layer n, we apply the time-domain weighted-sum operation to generate the timing tvj(n)+ and tvj(n)- for the positively and negatively weighted-sum calculation from the input layer, respectively. Then, these timings are directly transferred to neurons in the next layer p, and timing tvj(p)+ and tvj(p)- are obtained. Finally, we calculate the final outputs of the MLP using Equation 37 without calculating the middle layers' weighted-sum results using Equation 27.

We summarized the above mathematical time-domain operations in general MLPs graphically as shown in Figure 4. We refer to the “sum of the weights” as the “sum of the weights' absolute values” in the remainder of this paper. Note that the weights in the middle and output layers are replaced by the products of the original weight and the sum of the neuron's weights in the previous layer during the time-domain process. We indicated the sum of the new reconfigured weights by B instead of the aforementioned β, which indicated the sum of the original weights, as follows:

Note the bias of neuron j in layer n, whose index i = 0, is indicated as B0(n-1)w0j(n), in which B0(n-1)≡1. Therefore, the new weight connected from neuron i in layer n−1 to neuron j in layer n becomes Bi(n-1)wij(n). Then we can have the original weighted-sum result of the j−th neuron in the n−th layer indicated by yj(n) expressed as follows:

We performed numerical simulations to verify our weighted-sum calculation model. First, in order to verify our model for weighted-sum calculation with different-signed weights, we conducted a simulation to perform a weighted-sum calculation with 501 pairs of inputs and weights that consisted of 249 positive and 252 negative weights. We added a dummy weight to make the sum of positive weights equal to the absolute sum of the negative ones. Figure 5 shows the simulation results of the time-domain weighted-sum calculation with a dummy weight w_n+1. The results show that the weighted summation can be calculated correctly with different negative and positive firing timing inputs, each set of which are multiplied by the corresponding signed weights.

Then, we applied our model to a four-layer MLP (784-100-100-100-10) to classify the MNIST digit character set. We trained the MLP and then performed inference according to Equation 41 with the obtained weights, which were either binary (Courbariaux et al., 2015) or floating-point values. As described above, output spike timings at each neuron in the previous layer were directly conveyed to the neurons in the next layer without obtaining weighted-sum results in the middle layers. We found that we obtained the same weighted-sum calculation results in the last layer and also the same recognition precisions in both NNs as in the numerically calculated ones.

In the general time-domain weighted-sum neural network model as shown in Figure 4 and Equation 41, the weights must be reconfigured as Bi(n-1)wij(n) in order to generate two timings whose interval is proportional to the original weighted-sum result, which results in the same recognition accuracy as the original ANN. The reconfigured weights correspond to the PSP slope in the IF neuron model. The slope will be greatly increased with the reconfiguration, which may result in very high potentials that do not satisfy the hardware system criteria. To solve this problem, we introduced a scaling factor Γ⁽ⁿ⁾ for the n-th layer as shown in Figure 6, to adjust the PSP slope to a reasonable level. Note that every neuron in the same layer has the same scaling factor.

Then the reconfigured weight becomes Bsi(n-1)wij(n)/Γ(n), where Bsi(n-1) represents the scaled sum of weights in the previous layer n−1, and the scaled sum of the reconfigured weights in layer n, which is also interpreted as the total PSP slope, is expressed as

so we can obtain

Note that the bias bj(n) is reconfigured as

where Bs0(n-1)=1∏l=1(n-1)Γ(l). Accordingly, the original weighted-sum result is expressed as

From Equations 49, 41, we can find that the difference between timing tνj(n)- and tνj(n)+ remains the same before and after the scaling operations.

So far we have shown the general scaling process toward the weights' reconfiguration. Next, we will show some special cases that can simplify the weights' reconfiguration. Suppose that

meaning that the bias and the sum of the original weights of every neuron in layer n are equal to each other, such as in the BinaryConnect NN model (Courbariaux et al., 2015), whose weights and biases are binary values. Let the scaling factor Γ⁽ⁿ⁾ be

where βj(l) denotes the sum of the weights of the layer l(= 0, 1, 2⋯n) expressed as follows:

where βj=0(n)=1. Note that β1(n)=β2(n)=⋯=βj(n) under the assumption of Equations 51, 52. Then we can generate the desired timings using only the original weights wij(n),i≠0 shown in Figure 7a, without reconfiguring the weights (not biases included) as Bi(n-1)wij(n),i≠0 shown in Figure 4. However, the bias bj(n)must be reconfigured as

Accordingly, the original weighted-sum result will be

where β^(l) denotes the identical value of the sum of weights among neurons in layer l.

In modern deep neural networks with deep layers and a large number of parameters, several experiments using models without bias demonstrated that there was an accuracy degradation of 3.9% and 4% in CIFAR10 and CIFAR100 datasets, respectively (Wang et al., 2019). Such degradation of less than 5% is supposed to be acceptable when deploying DNNs to resource-constrained edge devices, in which trade-offs between accuracy, latency, and energy efficiency need to be carefully considered (Shuvo et al., 2022; Ngo et al., 2025).

We also trained a four-layer MLP (784-100-100-100-10) with and without biases on the datasets MNIST and Fashion-MNIST and compared the results in both the floating-point and binary weight connect models, as shown in Figure 8. The results showed that the accuracies with and without biases were comparable. Therefore, in certain cases, the bias can be removed so that the reconfiguration cost of the bias shown in Equations 48, 54 is saved.

We have shown a case in which the weights and biases were restricted to the condition shown in Equations 50, 51 so that the cost of the weights' reconfiguration can be saved. Next, we propose a method to satisfy the restriction in Equation 50 for a more general ANN model to save the weights' reconfiguration shown in Figure 7b. Note that we discuss the method in the model without biases for simplicity. We add a dummy weight to every neuron in layer n to make the sum of the weights identical. We regard the identical value in layer n as β⁽ⁿ⁾. The dummy weight to neuron j in layer n, indicated as dj(n), is allocated as:

Note that the input timings for the dummy weights dj(n) and -dj(n) are identical, such as T_in, meaning a 0 input.

From Equations 40, 41, we can find that the coefficients applied to the output timing difference are increased monotonically as the layer goes deeper. It has generally been observed that the outputs of every neuron, i.e., the weighted-sum results, converge at a certain range in a well-trained ANN. Therefore, we figure out that the timing difference decreases monotonically as the layer goes deeper. This effect essentially results from our calculating the positively signed and negatively signed weighted sums separately.

We demonstrate the timing difference issue by means of a case study in which we perform the time domain weighted-sum inference in a well-trained four-layer MLP (784-100-100-100-10). We collected the distributions of the output timing differences in every layer of the MLP when performing evaluation on the 10,000-sample test data in MNIST. Figure 9a shows the distributions where the histograms show only 100 of the total 10,000 samples, but the standard deviations σ are calculated over the total samples. The output timing differences, σ, of the 1st, 2nd, 3rd and 4th layers are 5.89e − 8 s, 5.91e − 9 s, 8.42e − 10 s, and 1.08e − 10 s, respectively, under the assumption of T_in = 1 μs. If we assume that the resolution time step is 10 ns by taking the noise of analog circuits into account, the great majority of the timing differences in the 2nd and the subsequent layers are less than the time resolution. Therefore, such a time-domain multi-layer model cannot be implemented into analog VLSI directly. We also conducted an experiment to evaluate the noise tolerance of the above model. In the experiment, we injected noise with different standard deviations σ to the output timing tν- and tν+, and evaluated the MLP recognition accuracy. The results are shown in Figure 10a. We can find that the accuracy deteriorates when the noise level is around 0.5 ns near the distribution σ of the 3rd layer. The model does not work when σ is over 5 ns near that of the 2nd layer.

In order to solve the problem of decreasing output timing difference, we can introduce an amplification component into our model, which can amplify the timing difference just before the timings are transferred to the next layer. To examine the effectiveness of this amplification function, we performed experiments in which we amplified the timing difference with different gains and evaluated the recognition accuracy with the critical noise injected. The results are shown in Figure 10b. We also plotted the output timing difference distributions in every layer under different amplifying gain conditions. Figure 10c shows the distribution standard deviations, and Figure 9b shows the histograms with a gain of 10. Note that in these experiments, we simply set the same amplification gains in every layer without optimizing the gains. We found that the recognition accuracy is comparable to that in the model without noise injected if we select a gain to make the output timing difference distribution σ of the last layer larger than the critical noise level, such as 10 ns. However, for more robustness, the distribution σ is supposed to be much larger than the resolution time step so that the gain can be 8–10. We verified the effectiveness of the amplification function and established the time-domain weighted-sum model with amplification components. In VLSI circuits, we can introduce a time-difference-amplifier (TDA) (Abas et al., 2002; Asada et al., 2018) component to amplify the output timing difference.

We propose a circuit architecture of a neural network based on our established weighted-sum calculation model which is suitable for our TACT approach, accommodating both positive and negative weights. The architecture is shown in Figure 12 and is composed of a crossbar synapse array acting as resistive elements, the neuron part functioning as thresholding and nonlinear activation, and the configuration part controlling synapses.

Figure 12a shows a two-layer MLP architecture described in Figure 3 whose input layer is modeled in Figure 2c in which each synapse has two sets of inputs and weights. Another type of input layer architecture of the MLP is shown in Figure 12b, as described in Figure 2b.

In Figure 12a, there are two inputs for each synapse circuit, which are t_i as the signal input and t_dmy as a dummy input in the first layer, and tνi+ and tνi- in the subsequent layers. Pairs of positive and negative timings are directly connected to the next layer without subtracting the negatively signed weighted results from the positively signed weighted results according to the theory explained in Section 3.2 and Figure 4. In the synapse array, the horizontal and vertical lines are referred to as “axons” of the previous neurons and “dendrites” of the post neurons, respectively. Suppose that each axon line has M synapse circuits, and each dendrite line receives N synapse outputs. A synapse cell is designed with two resistive elements and two pairs of switches. A set of two identical resistances represents the weight value. The resistive elements are expected to be replaced by resistance-based analog memories to store the multi-bit weights (Sebastian et al., 2020). We can assume that the upper-side axon is for tνi+ and the other is for tνi-, and the left-side dendrite is for a positive weight connection while the other is for a negative one. The two switches are exclusively controlled according to the corresponding sign of weights, which is controlled by the weight control circuit. By contrast, there is one input and one weight for each synapse in the input layer shown in Figure 12b, while a row of dummy cells with a dummy input is added to the synapse array conceptually according to Section 3.1. The resistances (d_i) of the dummy cell are theoretically set according to Equation 56.

In AIMC, the most common implementation of a signed weight w_i is using a differential scheme with two subweights wi+ and wi- such that

in which one is for positive weighted-sum and another is for negative one (Xiao et al., 2023; Aguirre et al., 2024). Here, we treat the following signed weight configuration as a special differential scheme (Yamaguchi et al., 2020; Kingra et al., 2022):

Subtraction to obtain the final weighted-sum result is commonly performed in either differential mode or common mode. In differential mode, the operation is carried out at two separate nodes within the peripheral circuitry (Guo et al., 2017; Joshi et al., 2020; Yamaguchi et al., 2020; Sahay et al., 2020). In common mode, the subtraction is performed at a single node based on Kirchhoff's law, using either bipolar (Wan et al., 2022; Aguirre et al., 2024) or unipolar inputs (Wang et al., 2021; Khaddam-Aljameh et al., 2022; Le Gallo et al., 2023). It's worth noting that common-mode subtraction with unipolar inputs generally requires a bi-directional peripheral circuit, capable of providing two voltages: one higher and one lower than the common node voltage.

Signed inputs for 4-quadrant computation can be implemented by applying opposite polarity voltage (Marinella et al., 2018; Le Gallo et al., 2024) or using differential pairs when the input is unipolar (Schlottmann and Hasler, 2011; Bavandpour et al., 2019a). Additionally, signed computations without adopting the above two designs need multiple phase modulations, like two phases in Kingra et al. (2022) for 2-quadrant MAC and four phases in Le Gallo et al. (2023) for 4-quadrant MAC.

With respect to the signed weight representation in our approaches, the configuration in Figure 12b is regarded as the special differential scheme described in the expression Equation 58, and that in Figure 12a restricts the two subweights to be identical. We term the latter configuration as a complementary scheme, distinguishing it from the general differential scheme. With respect to the signed input representation, we adopt differential pairs as in Bavandpour et al. (2019a). Our model with the complementary scheme can perform four-quadrant MAC computation in a single modulation without bipolar or bi-directional peripheral requirements.

The neuron part shown in Figure 12a consists of a thresholding block, such as a comparator, a ReLU block, and a post-processing block (PPB) after the ReLU block. ReLU block with input and output timings is shown in Figure 13a. The relationships between inputs and outputs are illustrated in Figure 13b, in which both output timings are set identical to tνi+ when tνi+>tνi-. The truth table is shown in Figure 13c and accordingly the ReLU activation function can easily be implemented by logic gates, as shown in Figure 13d. With such circuits, the nonlinear activation function ReLU can be implemented with low energy consumption operation. The PPB can be either a TDA circuit or a set of TDC and DTC to address the issue of timing difference shrinkage discussed in Section 4.2. The TDA is introduced to transmit the timings to the next layer directly in an analog manner, and the TDC and DTC are introduced to communicate intra-layers digitally. We leave the PPB implementation with high performance, such as high precision and low power, to be an open design problem in this paper.

We summarize the main differences of our complementary weight approach with respect to the previous similar research (Bavandpour et al., 2019a; Sahay et al., 2020), which are also partially inspired by our model (Morie et al., 2016; Tohara et al., 2016; Wang et al., 2018), as follows:

In order to evaluate the energy consumption and computation precision of our TACT-based circuit, we designed a PoC CMOS circuit equivalent to the RC circuit to perform the one-column (i.e., N inputs and 1 output) signed weighted-sum calculation whose synapses are in a complementary scheme. The resistive elements in the synapses are replaced by pMOSFETs. The comparator function in the neuron part is implemented by an S-R latch.

We propose SRAM-based synapse circuits to implement an IMC circuit for the computation shown in Figure 14a. It consists of a 1-bit standard 6T SRAM to save the sign of a weight, a pair of pMOSFETs assigned as M1 and M2 serving as the value of the weight, and four pMOSFETs assigned as M3- M6 functioning as switches controlled by the SRAM state. M1 and M2 are identical transistors and are biased with the same gate voltage, implementing the concept of complementary dummy weight introduced in the previous chapter. They serve as current sources operating in the subthreshold saturation region, showing a high impedance. M3-M6 switch the current to the dendrite line determined by the weight's sign according to the diagram shown in Figure 12a. As a PoC circuit, we implemented the BinaryConnect NN (Courbariaux et al., 2015) by limiting all the biases of the synapse pMOSFETs to be the same.

The main design parameters and simulation conditions are summarized in Table 1. We used the predictive technology model (PTM) 45 nm SPICE model for the design and simulation. Both the gate length and width of the synapse pMOSFET were 0.45 μm. Based on the size of the synapse pMOSFET, we estimated the parasitic capacitance of the axon line and the dendrite line based on 65 nm SRAM-based IMC circuits (Kneip and Bol, 2021). As a result, the parasitic capacitance of the axon line per cell, denoted as C_al, is around 0.88 fF, and the parasitic capacitance of the dendrite line per cell, denoted as C_dl, is around 0.87 fF. V_gs of the synapse pMOSFET is fixed at –0.34 V so that one synapse current I_s is around 11.5 nA under typical conditions. We set the typical supply voltage of the synapse array and the neuron part to be 1.1 and 0.75 V, respectively. And the threshold (V_TH) of the post-neuron (i.e., the S-R latch) is around 0.4 V typically.

With respect to the computation precision, we set the full-scale time window (T_in) to be 640 ns, and the effective number of bit (ENOB) to be 4 bit as the design target. Then the total capacitance of the dendrite line (C_DL) for MAC computation can be obtained by

C_DL includes the total parasitic capacitance of the dendrite lines, NC_dl, the input capacitance of the post neuron, C_i, and an extra load capacitor (C_l) which is needed under the given T_in and I_s conditions.

Analog computation suffers from analog nonidealities (ANIs) (Kneip and Bol, 2021). These ANIs limit the computation precision, leading to a degradation of the inference accuracy. We sketch the main ANIs on our synapse circuit shown in Figure 14b. All these ANIs may cause the output jitters illustrated in Figure 14c resulting in computation errors. We summarize them in Figure 14d classifying them by their stochastic or deterministic nature.

Because time domain computation is sensitive to PVT variations (Seo et al., 2022) and local device mismatch is dominant than the intrinsic noise (Kneip and Bol, 2021; Gonugondla et al., 2021), we mainly considered the local mismatch and the PVT variations here.

We conducted Monte Carlo simulations to evaluate the errors induced by the local mismatches. A set of Monte Carlo simulation waveforms is shown in Figure 15a, and the standard deviations (σ) vs. the number of the inputs, N, are shown in Figure 15b. The results showed that the σ scales roughly as 1N leading to higher precision for larger N (Bavandpour et al., 2019a).

Our approach is expected to have good immunity to the PVT variations. The error induced by PVT variation in both the synapse array and neuron part is common to both positive and negative dendrite lines, and thus can be canceled from the point of view of the timing difference. To verify the PVT variation tolerance, we conducted a simulation for N = 50 with process and temperature (PT) corners shown in Table 1, and changed the supply voltage of the neuron part to 0.65, 0.75, and 0.85 V. We supposed that the gate voltage of the synapse pMOSFET changed along with the supply voltage of the synapse part, and thus the V_gs of it is fixed. One MAC PVT simulation result is shown in Figure 15c. The synapse current I_s changed largely across the PT variations shown in Table 1, resulting in large variation of the single dendrite line output timings tν+/tν-. However, the variation of the difference between them was much smaller. We also checked the weighted-sum linearity against the ideal 16 levels with 1LSB = 40 ns under the PVT simulations. The simulated linearity result is shown in Figure 15d, indicating good linearity with the max peak-to-peak variation of 8.33 ns. Finally, we incorporated the PVT and Monte Carlo simulation results into a distribution shown in Figure 15e, indicating that the ENOB = 4 was well achieved. We summarized the potentially achievable MAC computation precision with the number of inputs increased to 256, as shown in Table 2.

With respect to energy consumption, an input voltage charges up the parasitic capacitance of the axon line, C_al, and then charges the capacitance C_DL via synapse pMOSFET. Therefore, total energy consumption due to the dendrite line (DL) charge and discharge, E_DL, is expressed by EDL=CDLVTH2, and it was 80.59 fJ when V_TH = 0.3 V and 143.27 fJ when V_TH = 0.4 V. And the total energy consumption per DL due to the axon line (AL) charge and discharge, E_AL, is expressed by EAL=NCalVdd2, and it was 53.24 fJ, where V_dd = 1.1 V.

As for the neuron part, which consists of an S-R latch and the output buffer, the energy consumption, E_NP, was about 216.91 fJ when the supply voltage was 0.75 V, and decreased to about 76.49 fJ when the supply voltage is 0.65 V.

As a result, overall energy consumption was 210.32 fJ per MAC with N = 50 when the supply voltage of the neuron part was 0.65 V. This implies that the energy efficiency is 237.74 TOPS/W (Tera-Operations Per Second per Watt). This efficiency is comparable to the state of the art of the analog MAC macros (Seo et al., 2022; Choi et al., 2023). We summarized the potentially achievable energy efficiency with the number of inputs increased to 256, as shown in Table 3.

Our purpose is to show the potential energy efficiency and computation precision of the TACT-based circuit, so we don't perform further design space exploration for optimizing the performance of the proposed circuit.