Figure 1 depicts the working memory network model that supports “focused” state (sustained neuronal firing) and the “unfocused” state (activity-silent working memory), which builds upon Manohar's working memory model (Manohar et al., 2019) by adjusting it to the form of Spiking Neural Networks (SNNs), thus endowing it with greater biological plausibility. The network comprises two distinct types of neurons: feature-selective neurons and freely-conjunctive neurons. Feature-selective neurons receive unique types of feature information such as colors, orientations, and locations. On the other hand, freely-conjunctive neurons encode a combination of simultaneously active features and establish an associative mapping to feature-selective neurons. Upon arrival of feature information stimulus, the membrane potential of the corresponding feature-selective neuron increases. As the potential of a feature-selective neuron approaches its threshold, the neuron fires a spike. The spike train generated by feature-selective neurons can be interpreted as sensory activation of feature information, and it is perceived by freely-conjunctive neurons. Initially, the synaptic weights between the two types of neurons are randomly assigned, reflecting the connection strength between neurons. As spikes arrive from feature-selective neurons, the membrane potential of freely-conjunctive neurons increases, eventually leading to firing. Synaptic connection strength changes according to the temporal relationship between pre- and post-synaptic spikes, in accordance with the Hebbian plasticity rule. Freely-conjunctive neurons also compete with each other through lateral inhibition and self-excitation, following the winner-takes-all (WTA) rule. Through this competition, only one neuron remains active in each feature dimension. The working memory network model includes two independent weight vectors connecting feature-selective neurons and freely-conjunctive neurons, which depend on the direction of spike propagation. In Figure 1, W_fc indicates the synaptic weight of the forward direction (feature-selective neurons to freely-conjunctive neurons), and W_cf indicates the synaptic weight of the backward direction (freely-conjunctive neurons to feature-selective neurons). During Hebbian learning, both feature-to-conjunctive synapses and conjunctive-to-feature synapses are strengthened for the winner among freely-conjunctive neurons, while they are weakened for other freely-conjunctive neurons. This process creates an synaptic mapping between the freely-conjunctive neurons and the feature information stimulus.

Figure 2 shows the sequence of neuronal events in working memory: encoding, attention, and retrieval. Step 1: sensory inputs (color: blue, orientation: +45 degrees, location: top right) are received by feature-selective neurons. Then, freely-conjunctive neurons perceive spike trains from feature-selective neurons. The freely-conjunctive neurons filled with light red indicate relatively lower and erratic firing rates. During this process, the freely-conjunctive neurons compete and encode the active features. Following this, each feature dimension has a single neuron that wins a competition, which can be seen as neuronal events of encoding in working memory. Step 2: the neurons filled with deep red indicate higher and more stable firing rates. Under the WTA rule, firing from the winner among the freely-conjunctive neurons is stabilized. Step 3: when the sensory input to the feature-selective neuron is withdrawn, the freely-conjunctive neuron that has been firing stimulates the feature-selective neuron through the conjunctive-to-feature synapses, this results in the firing of the feature-selective neuron and, in turn causes the freely-conjunctive neuron to fire through the feature-to-conjunctive synapses. The self-excitation synapse of the freely-conjunctive neuron enhances its firing through self-stimulation. This sustained neuronal firing can be considered as neuronal events of attention in working memory, which indicate “focused” state of working memory. Step 4: a new round of encoding and competition in the working memory network, and different freely-conjunctive neuron from the previous round may enter the “focused” state. Although the feature information from the previous round is not presented in the working memory network in the “focused” state, it remains encoded in synaptic weights as an activity-silent working memory in the “unfocused” state. Step 5: The providing partial feature information to feature-selective neurons, which reactivates the “focused” state of corresponding freely-conjunctive neurons. This can be considered as neuronal events of retrieval in working memory. Step 6: freely-conjunctive neuron reactivates original features, completing the process of associative recall. From a certain perspective, the activity-silent working memory in this model can be conceptualized as an associative memory with long-term information storage. Although working memory is typically regarded as a form of short-term memory, several studies suggest that associative memory with long-term information storage also contribute to working memory (Burgess and Hitch, 2005; Olson et al., 2005; van Geldorp et al., 2012). During working memory tasks, as many rounds of sensory inputs are applied, the synaptic mapping of activity-silence working memory may be interrupted by new feature information. This is attributed to the limited capacity of working memory, which is consistent with the concept of forgetting in working memory. Although sustained neuronal firing weakens and ceases during the bi-directional feedback between two types of neurons after a relatively short period of time, this process indicates a transition from the “focused” state to the “unfocused” state, rather than forgetting.

The cross-sectional structure of the Au/LNO/Pt memristor used in this work is shown in the inset part of Figure 3A. The insulating layer of the memristor is a Single-Crystalline LiNbO₃ (SC-LNO) thin film with the thickness of 30 nm. The cross mark in Figure 3B display the electronic behavior of LNO memristive conductance under appropriate spike trains applied to the memristor. The blue cross mark depict the LTP characteristic of the memristor. Positive pulse trains comprising 100 sequential 1.5 V pulses, each lasting 5ms, are applied to the top electrode (i.e., the Au electrode) of the memristor while the bottom electrode (i.e., the Pt electrode) is grounded, and the memristive conductance gradually increases, indicating that the memristor undergoes a SET process. The red cross mark depict the LTD characteristic of the memristor. Negative pulse trains comprising 100 sequential −1.5 V pulses, each lasting 5 ms, are applied to the bottom electrode (i.e., the Pt electrode) of the memristor while the top electrode (i.e., the Au electrode) is grounded, and the memristive conductance gradually decreases, indicating that the memristor experiences a RESET process.

In this work, a modified Yakopcic's generalized memristor model (Yakopcic et al., 2011) is used to fit the experimental data of the LNO memristor. The equation of the modified memristor model is as follows:

In Equation (1), the hyperbolic sinusoid function is used to fit the I-V relationship of the memristor, along with parameters a₁, a₂, and b. The state variable of the memristor is represented by x(t), which varies between 0 and 1. At x(t) = 0, the memristor's resistance reaches its maximum value, while x(t) = 1 corresponds to the minimum resistance. In contrast to the original Yakopcic memristor model, a parameter r is introduced in Equation (1) to represent the ratio of the highest resistance value to the lowest resistance value. The purpose of this modification is to adjust the resistance range of the memristor to fall within the range of experimental data and to prevent the occurrence of infinitely large or small resistance values. Equation (2) presents the function g(V(t)), which imposes a programming threshold on the memristor. The positive and negative thresholds are denoted by V_p and V_n, respectively, with adjustable parameters for the magnitude of the exponentials represented by A_p and A_n. The state variable motion is modeled by the function f(x(t)), which is expressed in Equations (3) and (4). The motion remains constant until the point x_p or x_n, where the rate of exponential decay is determined by α_p or α_n, respectively. The window function w_n(x, x_n) is utilized to ensure the boundary of the state variable motion, as shown in Equations (5) and (6). Additionally, Equation (7) models the state variable motion, with the direction of the motion represented by η in terms of the voltage polarity. Figure 3A shows the current-voltage (I-V) relationship of the LNO memristor model under a voltage sweep from −2 to 2 V for both experiment and simulation. The LTP and LTD characteristics of the modified Yakopcic's generalized memristor model are illustrated by the green and orange lines in Figure 3B, with the parameters used in this work listed in Table 1. Considering the inherent instability of Cycle-to-cycle and Device-to-device variations in practical memristors, 40, 10, 25, and 20% noise are introduced to α_p, α_n, A_p, and A_n, respectively. The errorbars on the green and orange lines represent the maximum conductance variations of the memristor after 100 sequential LTD and LTP pulses.

In this study, a simplified Hebbian learning rule is introduced as the synaptic plasticity mechanism for feature-to-conjunctive synapses and conjunctive-to-feature synapses, as illustrated in Figure 4. Long-term potentiation (LTP) and long-term depression (LTD) of synaptic weights are determined by the temporal relation between pre- and post-synaptic spikes. When the pre-synaptic spike is fired first and the post-synaptic spike is fired immediately within a time window of 2ms, the synapse exhibits LTP. When the post-synaptic spike is fired outside of this time window, either earlier or later, the synapse exhibits LTD. The strength of LTP and LTD is determined by the SET/RESET pulse width, denoted by time scalar T_p. The pulse width for SET is three times wider than that for RESET. v^ represents the direction of the pulse voltage, with the direction of SET being positive and the direction of RESET being negative.

To harness the LTP/LTD behavior of the LNO memristor, a dedicated synaptic weight update circuit has been designed and optimized based on our previous research (Hu et al., 2013). The synaptic weight update circuit is comprised of a single LTP module, a single LTD module, one memristor, and the peripheral circuit. Schematic representations of the LTP and LTD modules are shown in Figures 5A, B, respectively. The “PRE” and “POST” nodes are connected to the pre-neuron and post-neuron, respectively, while the LTP and LTD nodes represent the output generated by the temporal relation between pre-synaptic and post-synaptic spikes, as specified by the simplified Hebbian learning rule mentioned earlier. At the initial state, both “SP” and “SD” nodes are set to a low level. I₁ and I₃ function as inverters, while I₂ and I₄ function as NAND gates. When the pre-synaptic neuron fires, transistor MP₁ turns on, causing capacitor C₁ to charge up to V_dd, and as a result, the “SP” node rises to V_dd. The output of I₄ in the LTD module is held at a low level, which means that the LTD module is inactive while the LTP module is operating, and vice versa. When the LTP module is in operation, C₁ begins to discharge through transistors MN₁ and MN₂, with the discharge current being regulated by V_bp. The maximum duration for the discharge of C₁ is denoted as t_LTP, which represents the time window of the LTP. When the post-synaptic neuron fires within t_LTP, transistor MN₃ will be turned on, causing the charge to be redirected to capacitor C₂, and setting the “S” input of the S-R latch to a high level. As a result, the LTP output of the S-R latch will be in a “HIGH” state. When the LTD module is in operation, the “S” input of the S-R latch is immediately set to a high level, causing the LTD output of the S-R latch to be in a “HIGH” state. The only purpose of the discharge of C₃ is to deactivate the LTP module while the LTD module is in operation. The LTP/LTD output will remain in a “HIGH” state until a “Ctrl” signal arrives at the S-R latch, which in turn determines the duration of the LTP/LTD output.

The LTP and LTD outputs described above are utilized to implement a Hebbian learning rule in the synapse weight update circuit, as depicted in Figure 6. When the LTP output is in a “HIGH” state, transistors MN₇ and M₁₀ turn on, applying a positive voltage Vr to the memristor with the top electrode at high potential and leading to a SET process in the memristor. Similarly, when the LTD output is in a “HIGH” state, transistors MN₈ and MN₉ turn on, applying V_r to the memristor with the bottom electrode at low potential, leading to a RESET process in the memristor. The duration of the SET/RESET process is equal to the duration of the LTP/LTD output. When the LTP and LTD outputs are in a low state, their inverted outputs LTP¯ and LTD¯ are in a high state. As a result, transistors MN₁₁-MN₁₄ in the path between the pre-synaptic neuron and the post-synaptic neuron remain on, allowing pre-synaptic spikes to transmit to the post-synaptic neuron through the memristor. However, when the LTP or LTD module is activated, two of the transistors among MN₁₁-MN₁₄ turn off, and the path between the pre-synaptic neuron and the post-synaptic neuron is closed.

To achieve working memory, we utilized a spiking neural network with the winner-takes-all (WTA) functionality previously developed in our research (Wang et al., 2019). All synapses involved in working memory, including feature-to-conjunctive synapses, conjunctive-to-feature synapses, self-exciting synapses, and lateral-inhibition synapses, share the same synaptic architecture. The synapse weight of feature-to-conjunctive and conjunctive-to-feature synapses can be modified by the aforementioned synapse weight update circuit that utilizes a simplified Hebbian learning rule. On the other hand, the synaptic weight of self-exciting synapses and lateral-inhibition synapses remain fixed. Both feature-selective neurons and freely-conjunctive neurons in our network utilize the leaky integrate-and-fire (LIF) neuron model. The capacitor within the neuron integrates the input current from the synapses, causing the neuron's membrane potential to increase. Once the neuron potential reaches the threshold, the neuron fires a spike, and its potential returns to its resting state. The network topology of our working memory design, consisting of interconnected artificial neurons and synapses as illustrated in Figure 1.