HFNet: A CNN Architecture Co-designed for Neuromorphic Hardware With a Crossbar Array of Synapses - Gopalakrishnan, Roshan; Chua, Yansong; Sun, Pengfei; Sreejith Kumar, Ashish Jith; Basu, Arindam (Frontiers in Neuroscience, 2020)
The hardware-software co-optimization of neural network architectures is an emerging field of research with the advent of commercial neuromorphic chips such as the IBM TrueNorth and Intel Loihi. Development of simulation and automated mapping software tools in tandem with the design of neuromorphic hardware, whilst taking into consideration the hardware constraints will play an increasing role in deployment of system level applications. This paper illustrates the importance and benefits of co-design of convolutional neural networks (CNN) that are to be mapped onto neuromorphic hardware with crossbar array of synapses. Towards this end, we first study which convolution techniques are more hardware friendly, and propose different mapping techniques for different convolutions. We show that for a 7-layered CNN, our proposed mapping technique can reduce the number of cores used by 4.9-13.8 times for crossbar sizes ranging from 128x256 to 1024x1024, compared to the toeplitz method of mapping. We next develop an iterative co-design process for the systematic design of more hardware friendly CNNs whilst considering hardware constraints such as core sizes. A python wrapper was developed for the mapping process that is also useful for validating hardware design and studies on traffic volume and energy consumption. Finally, a new neural network dubbed HFNet is proposed using the above co-design process which achieves a classification accuracy of 71.3% on the IMAGENET dataset (comparable to the VGG-16) but uses 11 times less cores for neuromorphic hardware with core size of 1024x1024. We also modified the HFNet to fit onto different core sizes, and report on the corresponding classification accuracies. Various aspects of the paper are patent pending.