A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons - Akbarzadeh-Sherbaf, Kaveh; Abdoli, Behrooz; Safari, Saeed; Vahabie, Abdol-Hossein (Frontiers in Neuroscience, 2018)
Human intelligence relies on the vast number of neurons and their interconnections that form a parallel computing engine. If we tend to design a brain-like machine, we will have no choice but to employ many spiking neurons, each one has a large number of synapses. Such a neuronal network is not only compute-intensive but also memory-intensive. The performance and the configurability of the FPGAs make them the best hardware solution to deal with these challenges. This paper presents a scalable architecture to simulate a randomly connected network of Hodgkin-Huxley neurons. To demonstrate that our architecture eliminates the need to use a high-end device, we employ the XC7A200T, a member of the mid-range Xilinx Artix-7 family, as our target device. A set of techniques are proposed to reduce the memory usage and computational requirements. Firstly, the resource sharing is used to increase the number of neurons in the target FPGA. Our architecture consists of several identical building blocks called cores. Each core shares its resources among its assigned neurons. In addition, a piecewise-linear approximation method using the least square algorithm is exploited to improve both the performance and the area of the steady-state values and inverse time constants of the gating variables. Furthermore, we design a hardware to generate the connectivity vector on the fly instead of storing it in a huge memory. Moreover, to reduce both the resource usage and the computational latency even more, an approximate two-level counter is introduced to count the number of the spikes at the synapse for the sparse network. Last but not least, a 7-stage pipeline is utilized to increase the throughput in exchange for a small increase in the resource consumption. These techniques make it possible to have a high-performance scalable architecture, which could be configured for either a real-time simulation of up to 5120 neurons or a large-scale simulation of up to 65536 neurons in an appropriate execution time on a cost-optimized FPGA. Our approach also brings the large-scale spiking neural networks to the embedded systems.