Details of resistance switching in intrinsic oxide RRAM devices may be found elsewhere (Mehonic et al., 2012a,b, 2015, 2016, 2017) but to briefly summarize, application of an initial electroforming field, limited to prevent catastrophic dielectric breakdown, across a pristine, highly insulating, oxide generates a filament of conductive oxygen vacancies bridging the oxide film. Subsequent application of a field, either of the opposite polarity (bipolar operation) or similar polarity (unipolar) without a current limit resets the device to a high resistance state. Applying a field of the original polarity (bipolar operation) or the same polarity with a current limit (unipolar) sets the device back to the low resistance state. Devices may typically be cycled between the high and low resistance states many times.

Figure 1A shows a typical unipolar resistance switching of the devices we use in this study. The electroforming process typically occurs around 6 V, while the set and the reset voltages are typically 4 and 2.5 V, respectively. For the electroforming and the set process, a current limit of 3 mA is used to prevent hard breakdown. Similar to other RRAM devices, SiO_x unipolar devices show a variability of the switching voltages. This is shown in the cumulative plots in Figure 1B, in which data is obtained from more than 1,000 I/V sweeps (top contacts size 200 × 200 μm).

Devices may be set or reset depending on the shape of voltage pulses. Devices may be set by an ascending sequence of 300 ns voltage pulses, which, over a sufficiently long time, look like the leading edge of a voltage pulse, and then they may be reset in response to a descending sequence of pulses that look like the trailing edge of a triangular or sawtooth pulse. The gradual resistance change can be tracked by applying short read voltage pulses (0.6 V, 300 ns) that do not induce any switching (shown in in Figure 4). These pulses were applied in between each of the ascending or descending pulses that make up the sawtooth voltage ramp (Figures 2B,C—shown as a continuous blue line for clarity) while the current supplied by the Keithley system was measured, and hence the device resistance obtained. The transition from LRS to HRS begins to occur at around 2.7 V, a voltage that agrees well with the statistical measurements we carried out shown in Figure 2B. The ascending pulse train can then set the device to a LRS (Figure 2C). Resistance gradually decreases as the voltage bias increases, which demonstrates the system's capacity to exhibit plasticity. An important feature is that the resistance value for any SiO_x device can be incrementally adjusted by controlling the initial resistance state, voltage starting position and cut-off voltage of the pulse train.

That the sign of voltage pulse gradient control both setting and resetting processes in our devices suggests that combining suitable tailored pulses and applying these to individual devices may allow us to emulate STDP in biological synapses. In this study, external circuitry is used to provide programming voltage pulses, but it should be borne in mind that they may in principle be generated by optimized unipolar devices, as we have previously demonstrated (Mehonic and Kenyon, 2016).

STDP is a form of Hebbian learning rule that results in synaptic modification based on the relative timing of pre- and post-synaptic voltage spikes (Hebb, 1949; Bi and Poo, 1998; Abbott et al., 2000; Jo et al., 2010). That is to say, the relative arrival time of two spikes (“pre-synaptic” and “post-synaptic”) at the synaptic gap determines whether the synaptic strength will be increased, decreased, or remain unaltered. The change of state in a biological synapse is represented the change in excitatory postsynaptic current amplitude; in a RRAM device this change is represented by the change in device conductance (Chua, 1971).

In order to control both setting and resetting processes we need to design suitable voltage pulses and to vary the delay between “pre-synaptic” and “post-synaptic” pulses. We chose two different combinations of pulse shape to test the STDP properties of our devices, with programming pulses being the sum of distinct pulses with variable inter-pulse delays. Figure 3 illustrates the concept of changing device conductance by tailoring pulse shape. In the first case, we used square and triangle pulses as the pre- and post-synaptic spikes, respectively (both 1.5 V, Figure 3A). To ensure that the transition point between setting and resetting is at zero the triangle pulse had different rise and fall times (Figure 3A). The leading edge of the triangle pulse was set to be equal to the duration of the square pulse. When the applied pulse, or combination of pulses, is below a threshold voltage, V_th, there is no change to the device conductance. However, for pulses above V_th, the device conductance will change dependent on the sequence of voltages applied to the device. In the case of a slowly rising pulse, the device will SET into a low resistance state once the threshold is reached. Rapidly reducing the voltage has little effect, and the device remains in the LRS. However, if the pulse has a sharp leading edge and a slow trailing edge, the integral of current flowing through the conductive filament can become high enough to generate sufficient Joule heating to rupture the filament. The device therefore enters the HRS. In Figure 4 we present an example of 12-cycle set of combined pulses for a non-identical pulse configuration. Each subsequent pulse has the delay between pre- and post-synaptic pulses reduced by 90 μs, and hence the resultant pulse shape changes from square followed by triangle to triangle followed by square. At intermediate delays we can see the device under test initially setting to a LRS and then resetting to a HRS. Device resistance is thus dependent on the time difference between the two pulses. As was predicted, a rising edge above V_th lowers the resistance of the device under test, while a gradually descending voltage edge above V_th increases it.

In order to generate an STDP-like response with nominally identical pre- and post-synaptic pulses we used two square voltage pulses and modified the post-synaptic pulse with a capacitor; this is a scheme that may easily be implemented in a real system. Our previous work has demonstrated how voltage spikes can be generated by individual RRAM elements, and it would be straightforward to combine these with appropriate capacitive elements. The result is a modified square pulse that looks more like a triangular pulse. This allows us to exploit the previously-shown device response to different leading and trailing pulse edge slopes. To achieve the required gradient we emulated the response of a 3 μF capacitor, but it should be noted that much smaller capacitance values will be sufficient for devices operating in the nanosecond regime rather than the microsecond regime studied here for demonstration. The square pulse peak voltage remained the same at 1.5 V, and the pulse width was 450 μs. The shift that was previously required for a non-identical configuration was no longer needed due to the modification of the post-synaptic pulse. Figure 4B shows an example of a sequence of 11 pulses. The DUT shows similar behavior to the previous setup, and we are able to demonstrate that this pulse setup mimics biological STDP (Figure 5).

We conducted a statistical analysis of the second pulse configuration (square pulse and modified square pulse). The results in Figure 5 are based on 306 pulse cycles identical to those represented in Figure 4. Before applying the pulse trains the devices were electroformed to a preconfigured resistance of ~2 kΩ. The pre-configuration routine is necessary to force a conductive filament into a metastable state whose conductance can be either increased or decreased by the appropriate voltage pulse combination. If the filament were in a very high resistance state, for example, further increases in resistance would not be possible. To investigate the statistical significance of timing-dependent changes in conductance, we determined the success rate of expected occurrences (Figure 5A). Here we measured for the same 306 pulse cycles the probability of a negative difference in pre- to post-synaptic pulse timing resulting in a positive change in synaptic weight (conductance), and vice-versa for positive differences in spike timing. We find that nearly all instances had a success rate >50%, indicating the statistical favorability of STDP-like behavior. The median of synaptic weight change (i.e., change in device conductance) is plotted against the relative time delay between pre- and post-synaptic pulses shows a striking similarity to biological STDP (Figure 5B). There is a transition at small positive delays that mimics biological behavior. Figure 5C shows the mean percent change in synaptic weight (conductance) versus time delay between pre- and post-synaptic spikes. In this case, we selected those instances of successful change in synaptic weight and constructed an STDP response curve. We have thus a proof-of-principle demonstration that not only it is possible to achieve STDP behavior, but also it is a statistically favorable process. We note at this point that the unsuccessful STDP events in our non-optimized devices are primarily related to the variability in set and reset voltages. This stochasticity may be greatly reduced through material optimization and device design, as we have recently demonstrated in RRAM devices for non-volatile memory applications. We are therefore confident that further work will improve substantially the success rates demonstrated here.

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.