In BN, total power dissipation consists of a static and a dynamic part. The major factor of static power dissipation in neuron cells is due to Na-K pumps maintaining a constant resting potential value, despite the sodium and potassium leakage currents. In the circuit design domain, optimizing static power consumption imposes low DC voltage supply and transistors featuring small gate widths.

The dynamic part of energy dissipation is due to the Action Potential (AP) or “spike” generation and propagation. In BN, the AP corresponds to a rapid voltage change between extra and intra-cellular spaces, which are separated by the (quasi-) insulating lipid bilayer. According to the reference model of charge transfer, the two-ion model (Hodgkin and Huxley, 1952), the rising part of the spike is mainly due to an inward sodium current, while the decreasing part is due to an outward potassium current. Changing the voltage across the membrane capacitance C_m by ΔV, will need, at least, an amount of charge ΔQ = C_mΔV to move from one side of the membrane to the other. Since the driving potentials on both sides of the membrane (the Nernst potentials) are constant, the minimum energy dissipated for this change will be ΔE = ½C_mΔV². If we consider the generation and propagation of a spike (charge and discharge), the total energy dissipated by the cell will be at least C_mΔV².

The driving force for the inward and outward currents are the Nernst potentials E_na and E_k, which are almost constant in time. In living beings, E_k varies from −80 to −100 mV, while for E_na it is from +30 to +55 mV (Hodgkin and Huxley, 1952; Morris and Lecar, 1981; Wei et al., 2014). The membrane potential always stays between E_k and E_na and in vivo measurements showed that the resting potential is close to E_k while the ΔV for a spike is close to 100 mV (Hodgkin and Huxley, 1952). Using ΔV = 100 mV and C_m = 245pF (Hasler and Marr, 2013) means at least 1.5 × 10⁸ sodium (resp. potassium) ions are entering (resp. leaving) the neuron at each AP and the corresponding energy loss is about C_mΔV² = 2.45 pJ.

Starting from these simple considerations, it is clear that decreasing the dissipated energy in AN passes from setting C_m and ΔV to the smallest possible values. For artificial neuron circuits, the spike amplitude is proportional or strongly related to the applied DC voltage (Indiveri et al., 2011). Usually, the DC voltage of these circuits is about 1V. Since the energy loss varies with ΔV², the smallest possible value for ΔV is desired. Meanwhile, maintaining compatibility with the biological neuron spike amplitude, a feature of interest for some applications, entails fixing ΔV to about 100 mV. This implies a DC supply voltage of about 150 to 200 mV and constitutes a strong constraint on the active devices comprising the circuit. In particular, the transistors should operate in deep subthreshold regime characterized by a gate voltage far below the threshold, which currently varies between 0.3 to 0.5 V for advanced fabrication nodes. In this regime, however, MOS transistors show some interesting characteristics, such as the exponential control of the drain current by the gate voltage, a low current and therefore low energy dissipation, but they also present some drawbacks, such as a limited transconductance leading to extremely low voltage and power gains.

The other parameter targeted for low energy dissipation is the membrane capacitance. In artificial neuron circuits three main components can be distinguished: the discrete capacitance added in the circuit, and the parasitic capacitance of interconnects. The gate capacitance of transistors was found negligible for the small transistor sizes used in this work. Since the membrane capacitance value has a strong impact on several circuit parameters (energy loss, membrane charging and discharging times, spiking frequency, membrane voltage noise), its value is of utmost importance. For this reason, a mathematical model for the neuron is necessary to provide the necessary guidelines for circuit design.

The implementation of an artificial neuron circuit is defined by the selection of a corresponding mathematical model. An analysis of the various advantages and drawbacks of the different mathematical neuron models was proposed in Izhikevich (2004). The Leak Integrate and Fire (LIF) model is one of the simplest and most widely used for such implementations (van Schaik, 2001; Indiveri et al., 2011). However, it is not biophysically realistic: it does not accurately represent the dynamics of ion transport through the neuron membrane. In the analysis of Izhikevich (2004), it was shown that from a biophysical standpoint two models were meaningful: The Hodgkin-Huxley (HH) model (Hodgkin and Huxley, 1952) and the Morris-Lecar (ML) model (Morris and Lecar, 1981). The HH and refined-HH models (Wei et al., 2014) are considered as reference for in depth analysis of the neuron non-linear behavior. Nevertheless, the connection between the HH model and transistor physics is not easily discernible. When transferred to the circuit domain, the use of four non-linear differential equations and multiple non-linear parameters would lead to a relatively complicated topology, demanding considerable silicon surface (Yu and Cauwenberghs, 2010). On the contrary, the ML model is much more attractive for this purpose (Patel and DeWeerth, 1997). It is compiled as a system of two non-linear differential equations associated with exponential functions (Equations 1–5).

In the above equations the symbols are explained as follows: C_m is the membrane capacitance, I_ex is the excitatory current, E_K, E_Ca, and E_L, are the ion equilibrium potentials, G_Ca, G_K, G_L are the Ca, K and leak conductances, n_ss and m_ss are the steady-state potassium and sodium gating variables, λ₀ is the reference frequency and V₁₋₄ are fitting parameters that can serve for tuning the dynamic properties in order to represent different systems of interest.

The ML model features only two state variables: the membrane voltage V_m and the potassium gating variable n. It is well suited to perform phase plane analysis, an efficient tool for analyzing the non-linear dynamics of neurons in terms of stability, spiking conditions and spiking modes (Izhikevich, 2007). Acknowledging this fact, the next section details analytically the design of a circuit response approximating the ML equations. Though exact 1-1 circuit representation of the ML equations is not pursued, this approach yields an energy-efficient design, whose response achieves a good correlation with a higher-order cortical neuron model (Section Biomimetic neuron). As the ML model was initially conceived referring to a barnacle muscle, the following analysis uses Na and K ions (instead of Ca and K) aiming to indicate in the notation the neuronal context, which is ultimately addressed.

Expressing the system of equations of the ML model as a circuit response can be carried out through a series of considerations for the various components of the system. The most apparent involves the two differential equations to be represented by expressions based on current node summation, as per Kirchhoff's Current Law (KCL). Also, Na and K channel dynamics can be represented by single transistors biased in subthreshold, as it has been previously shown (Farquhar and Hasler, 2005; Hynna and Boahen, 2007).

Figure 1 shows the proposed neuron circuit, based on the ML model described above. The membrane capacitance, C_m, is charged through MP_Na (a PMOS transistor modeling the sodium channel) and discharged through MN_K (an NMOS transistor modeling the potassium channel) and the leakage conductance G_L. The membrane voltage node is the summing point of the excitation current, leak currents as well as two feedback loops: A positive feedback loop through MP_Na and MP₁/MN₁, which implements a pull-up network for V_m, and a negative feedback loop, which implements a pull-down network through MN_K and the two cascaded inverters MP2/MN2 and MP3/MN3. The time constant of the negative-feedback loop is set by capacitance C_K.

The excitation current I_ex is assumed to be provided by a synaptic circuit, which in the most rudimentary form can be implemented by a single transistor current source.

The circuit analysis for the proposed circuit is divided in three parts: the drain current model, the static properties of inverters in subthreshold operation and the circuit response equation.

If biological accuracy is not of prime concern it could be traded-off for a reduced silicon footprint and a high output frequency performance. Such a modification is suggested in Figure 4. In this circuit, the characteristics of the feedback loops (dynamics, threshold voltage etc.) cannot be set independently, because of the presence of a common inverter stage MP₁/MN₁. Further simplification is obtained by the removal of the leak conductance. The resulting circuit response might not reach the biological relevance of the initial circuit, yet it is still interesting, especially when combined with low capacitance values. Such a lightweight configuration, referred as “simplified neuron” in the following, could adhere to a wider range of frequency specification, aiming at potential deployment in SNNs for computational applications. As it is exhibited below, though the original spike form is not retained and initial design flexibility is compromised, the spiking nature of the output remains intact and maximum output frequency is increased by two orders of magnitude with respect to the biology. Obviously, the approach in circuit analysis seen above is still valid.

The ML neuron circuits described in the preceding sections have been designed and fabricated using TSMC 65 nm CMOS process in the LP option. The test chip size was 1.2 × 2.1 mm and comprised a variety of neuron circuits including variants of the aforementioned biomimetic and simplified neuron topologies. The area occupied by a single neuron circuit ranges from 35 μm² for the simplified neuron to 200 μm² for the biomimetic version without accounting for the output driving buffer or protection circuitry. The capacitors typically dominate the area utilization: 65% for the simplified and 70% in the biomimetic version. A photograph of the fabricated chip is shown in Figure 5. The designs presented here are highlighted.

All the neuron circuits were designed with external biasing. The excitation was implemented with on-chip externally biased transconductance. The output was monitored through an on-chip unity gain output buffer that was designed ensuring that the frequency response of the neuron circuit would not be affected. The output buffer featured independent DC supply to enable accurate power consumption measurements while the neuron's bias pins were not ESD protected. Concerning the results presented in the following section: static power refers to a zero excitation condition, while dynamic power consumption is deduced from the consumption under constant excitation, which induces a spiking output.

The experimental set-up was composed of a waveform generator that generated step signals for the neuron excitation. The supplies used for biasing enabled measurement of the average current with a nominal 500 fA accuracy. The output signal issued from the buffer was monitored by an oscilloscope, in order to perform spike width, frequency and amplitude measurements.

To supplement the mathematical analysis above with more intuition, circuit operation can be clarified by following the circuit dynamics for the membrane voltage (Figure 6A) and the drain currents of MP_Na and MN_K transistors (Figure 6B). The following description applies to both presented variants equally.

When excitation is not present, a constant membrane voltage V_m is obtained, assuming a stable circuit. This constant voltage is known in neuron physiology as the resting potential V_rest. In BN, this value is close to the potassium Nernst potential. For the circuit, this means that V_rest should be essentially pulled down close to the negative supply. This is achieved by proper sizing of the transistors representing the ion channels. The conductance of MN_K should be much higher than the one of MP_Na, in order to achieve a small voltage drop across MN_K source and drain terminals.

While in a rest state, with V_m close to the negative rail, there exists a small current through MN_K and MP_Na. Adding an excitation current I_ex will induce further charge accumulation in C_m. However, if this current is not sufficient to overcome the current that can be sustained in the MN_K branch, then due to its partial compensation, V_m will be slightly increased on a higher level than the initial resting potential, but still remain constant. On the contrary, if the excitation current exceeds this limit, this will cause V_m to increase with a slope proportional to the excess current: this situation is illustrated in Figure 6A by the quasi-linear increase of membrane potential after 100 μS. If the duration of this excitation is enough to reach the switching threshold of the first inverter (MN1/MP1), the output will exhibit a steep ascent through the positive feedback action of MP_Na. This happens in the vicinity of −40 mV in Figure 6A. This steep increase is due to the exponential relationship between the drain current of MP_Na and its gate voltage, V_GNa.

Following the increase, as V_m approaches the positive supply value, the source-drain voltage of MP_Na decreases. This will effectively limit the rise of V_m, because the current though MP_Na diminishes as shown in Figure 6B. In the mean-time, another phenomenon takes place. As V_m rises, capacitor C_k is charged and the drain current of transistor MN_K is increased. This action acts antagonistically to the reason creating it, i.e., to the rise of V_m, therefore constituting negative feedback. V_m reaches its maximum value when the drain currents of MP_Na and MN_K are equal. After this point the increase in the MN_K drain current will discharge the membrane capacitance, returning V_m eventually back to its resting value or, depending on the excitation, to a value where the current charge accumulation in C_m recommences.

As mentioned before, the above described dynamics and the output spike form rely mainly on circuit characteristics such as the conductance ratio of MP_Na and MN_K, the switching threshold of the inverters, as well as the values of the associated capacitances for C_m or C_k. For the biomimetic version of the proposed circuit, the facility to independently configure the gains and the time constants for the antagonizing loops ensures tuning of the output form parameters, such as the resting potential, the spike amplitude and width, the spiking frequency and the range of the excitation current. This flexibility permits approximating the behavior of biological neuron models, as it is shown in the following paragraph.

For various applications (robotics, medicine…), the neuron circuit dynamics should be compatible with the ones of BN. To account for their different characteristics, a reference model proposed in Wei et al. (2014) was used. This model can be considered as an improved Hodgkin-Huxley model, which unifies neuronal dynamics from spikes to seizures using four state variables, aiming at a better understanding of some pathological states. To achieve a compact circuit and low energy dissipation for the biomimetic circuit variant, capacitance values of C_m = 50 fF and C_K = 100 fF were used with no leak conductance introduced to the circuit. The leak component of the ML equations, however, exists in the form of the parasitic leakage current of the transistor MN_K. As it can be easily observed, an extra component modeling the leak has the same effect as increasing the size of the transistor MN_K (KCL at Vm node in Figure 3). The absence of an explicit component does not compromise the approximation of the mathematical model, but rather limits the available parametrization options. The “ionic” transistor widths were set as W_Na = 0.6 μm and W_K = 1.83 μm and circuit time constants in the millisecond range were achieved. The rest of the circuit parameters can be found in Table 1.

The comparison between the circuit simulation (A), the reference model (B) and the experiment (C) is illustrated in Figure 7. The Nernst potentials (+55 mV, −92 mV) were applied for circuit biasing, while the reference model plots were created with the code offered with Wei et al. (2014). For the measured results, VSS was set to ground and the supply voltage to 200 mV. The neuron circuit and output was monitored through a buffer. In this comparison, an excitatory pulse current is applied for Ts = 10 ms. Since the reference model is based on normalized quantities per unit area (I_ex = 20 μA/cm² and C_m = 1 μF/cm²) a common normalization coefficient, ξ = I_ex/C_m, is used. Figure 7 shows that very similar responses are obtained. For each case, three spikes are generated during the excitation. A slightly decreasing spike amplitude is observed for the reference model, while a constant amplitude is observed for the circuit. The form of the first spike in the measurement differs due to the initial condition imposed by the excitation. Below the supply value of 200 mV, no spikes were observed. This is attributed to the lower transistor currents observed in the experiment, giving rise to a reduced voltage gain (a sufficient voltage gain is required for spiking, as explained in Section Static properties of inverters in subthreshold).

In order to analytically compare the simulation and the experimental results with the reference model, three parameters have been considered: the spiking time S_t (defined as the latency between the maximum of each AP and the beginning of the excitation), the peak to peak amplitude, V_pp, and the spike width, S_W, defined at V_pp/2. These parameters are given in Table 2.

In the reference model, V_pp varies from 116 to 99.7 mV while the biomimetic neuron generates spikes with constant peak-to-peak amplitude of 120 mV. This difference is due to the use of the Morris-Lecar model based on two state variables, instead of the four state variables for the Wei model. Nevertheless, a good agreement is observed between the biomimetic neuron circuit and the reference model as far as excitability and spike shape are concerned.

Figure 8 shows the excitability of the biomimetic neuron. The minimal observed frequency is around 20 Hz. As expected, the firing rate and power consumption increase with the excitatory current. For I_ex = 120 pA, a maximal spike frequency of 1.2 kHz was obtained with a total dissipated power of 90 pW. According to Izhikevich (2007) this biomimetic neuron is categorized as a Type I neuron.

The energy efficiency of the circuit is deduced from the power dissipation and frequency measurements. In Figure 9 it is plotted as a function of the excitation current for two cases: (i) when the whole average power (static and dynamic) is taken into account and (ii) when the standby power (i.e., power consumption at zero excitation current) is subtracted. For an excitation current higher than 30 pA, the dissipated energy per spike is roughly constant and therefore independent of the spike frequency. An energy efficiency value of 40 fJ/spike is obtained when considering the dynamic power consumption.

It is worth mentioning that this value is several orders of magnitude lower than the energy efficiency of actual BN, as it is estimated in the 10 pJ range, from the ATP consumption in Attwell and Laughlin (2001), Lennie (2003) and Poon and Zhou (2011). This low energy dissipation obtained for the proposed AN can be interesting for SNN applications needing the integration of a large number of neurons.

In this part, the acceleration factor compared to the biological real time (BRT) and the energy dissipation are investigated for the simplified neuron design. Indeed, an important aspect of the simplified neuron, described above, is the ability to operate at accelerated biological time i.e., at higher frequency than the one of the BN. In this context, a circuit was sized to reach the highest spike frequency combined to the lowest energy dissipation. For this purpose, the supply voltage VDD = 200 mV and VSS = 0 V was applied and special emphasis was made to downscale the transistor size: the gate widths were chosen in the sub-micron range (few 100 nm). According to the aforementioned constraints, ultra-low capacitance values were chosen for C_m and C_k values, (4 fF and 8 fF, respectively including parasitic capacitances associated to the interconnections).

The output waveform resulting from an excitatory pulse current is presented in Figure 10, demonstrating the ability of this neuron to be externally stimulated.

In order to analyze the AN performance, both the spike frequency and the corresponding average power consumption (including the static and dynamic parts) have been measured as a function of the excitation current. For the maximum excitation current, a spike frequency as high as 26 kHz was obtained with a total power consumption of 105 pW. The plot of power consumption and spike frequency is shown in Figure 11 as a function of the excitation current.

As already discussed, the main objective of this work was to minimize the energy dissipation: a value is in the fJ/spike range was predicted by the circuit simulation. The energy efficiency was determined from measurements of the total dissipated power along with the spike frequency.

The energy efficiency is plotted as a function of the excitation current in Figure 12 in two cases as previously mentioned for the biomimetic variant of the circuit. The curves demonstrate that the energy efficiency does not significantly depend on the output spiking frequency and the experimental dissipation reaches values as low as 3 fJ/spike when only the dynamic power is considered.

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.