The high-k dielectric metal oxide (MO) plays a pivotal role in developing memristive devices with stable switching responses for various potential applications including data storage (Furber, 2016), multi-bit storage (Jeong et al., 2016), artificial synapses (Jeong et al., 2016), analog/neuromorphic computation (Kumar et al., 2022a) and in-memory computation (Mehonic et al., 2020). These oxides-based memristive devices are fully capable of adopting the existing standard complementary metal oxide semiconductor (CMOS) fabrication process which further enhances their acceptability and integration with CMOS technologies in current and future electronic systems (He et al., 2021). Importantly, high-k MO-based memristive devices are efficiently realized aforementioned applications (Furber, 2016; Jeong et al., 2016; Kumar et al., 2022a; Mehonic et al., 2020) due to their unique properties such as non-volatility (Zidan et al., 2018), nanoscale device scalability (Kim et al., 2021), ultrafast switching speed (Torrezan et al., 2011) and atto joule (aJ) energy and femto watt (fW) power consumption (Choi et al., 2016; Chen et al., 2020). Considering these benefits, scalable memristive devices can be a forefront solution in future computing technologies (Singh et al., 2025). However, the variability factor in device switching parameters such as switching voltages, ON/OFF ratio, and conductance levels, either in device-to-device (D2D) or in cycle-to-cycle (C2C) (Amirsoleimani et al., 2020; Zhang et al., 2019), poses a significant challenge to the wider acceptance of this memory technology.

These variabilities or inconsistencies could hinder their integration into future cutting-edge applications, including advanced memory technologies (Xia and Yang, 2019), in-memory computation (Xia and Yang, 2019), and neuromorphic computing architectures (Xia and Yang, 2019).

Previously, several attempts have been made to realize the high-k MO-based bilayer memristive devices with different electrode configurations including Pt/Ta₂O₅/HfO₂/TiN (Ghenzi et al., 2024; Ryu et al., 2021). Ghenzi et al. (2024) have demonstrated heterogeneous reservoir computing wherein, HfO₂ (10 nm) was grown by using thermal ALD at 280°C while Ta₂O₅ (10 nm) was deposited through plasma-enhanced ALD at 200°C. However, due to the process variations and growth temperature difference, fabricated memristive devices exhibited high switching voltages (<10 V) with inconsistency in the resistive switching responses (Ghenzi et al., 2024). Ryu et al. (2021) have also reported Pt/Ta₂O₅/HfO₂/TiN-based memristive structure to implement long-term and short-term plasticity wherein, HfO₂ (5 nm) was grown via thermal ALD at 250°C while Ta₂O₅ (15 nm) was deposited through reactive DC magnetron sputtering at room temperature. However, the reported outcomes revealed that the device switching voltages showed comparatively high values of C _V in V _SET (6.78%) and V _RESET (4.78%) which could be due to the utilization of two different deposition systems and growth temperature that led to the anomalies and irregularities on the device surface (Ryu et al., 2021).

Napari et al. (2024) have reported a TiN/HfO₂/Ta₂O₅/TiN-based memristive device structure in which Ta₂O₅ (5 nm) was deployed using plasma-enhanced ALD at 200°C while HfO₂ (3 nm) was grown by thermal ALD at 175°C. However, the obtained data show that device performance is not very stable with a weak memory window and the detailed statistical analysis has also not been discussed (Napari et al., 2024). Recently, Kumar et al. (2025) have demonstrated TiN/HfO₂/Ta₂O₅/TiN-based standalone memristive devices through a single thermal ALD having a memory cell size of 400 μm². In this reported work, the impact of a thin Ta₂O₅ (2 nm) layer was investigated in HfO₂-based memristive devices. Additionally, the reported work (Kumar et al., 2025) experimentally demonstrated that the origin of switching was resistive rather than capacitive through impedance spectroscopy analysis (Kumar et al., 2025). Considering the aforementioned experimental reports (Ghenzi et al., 2024; Ryu et al., 2021; Napari et al., 2024), utilization of two different deposition systems and variation in growth temperature could introduce surface/interface anomalies which further deteriorate the device performance. Therefore, to avoid these issues, we have utilized a single thermal ALD system with constant growth temperature for both oxide layers which significantly improves the statistical performance of the fabricated devices in the crossbar array configuration.

Herein, we have thoroughly electrically characterized the randomly selected memristive devices from a large-scale wafer (6-inch diameter having total devices of ∼100 k in the crossbar configuration) and examined their resistive switching responses and values of variability factor in the device switching parameters. The selected memristive devices exhibit bipolar switching responses with excellent stability and show 22.72% (V _SET) and 15.72% (V _RESET) variations in the device switching voltages corresponding to the maximum switching voltages of the tested devices. Moreover, time series analysis (TSA) is employed by considering the device switching voltages (V _SET and V _RESET) to predict the device’s performance. TSA is a robust statistical and well-recognized method for analyzing data collected at regular intervals which facilitates the investigation of inherent patterns and trends in datasets. The obtained outcomes are well matched with the experimental data which further shows the efficiency of the utilized model. Additionally, the devices depict the lowest value of the coefficient of variability (C _V) in both D2D (3.22%) and C2C (1.76%) in device switching voltages. Additionally, the fabricated memristive devices successfully emulate the synaptic functionalities including potentiation (P), depression (D), paired-pulse facilitation (PPF), and paired-pulse depression (PPD), and synaptic response having a least value of nonlinearity (NL) factor of 0.43 close to the ideal value of NL in biological synapses (Kumar et al., 2022a).

The detailed fabrication process flow for bilayer (HfO₂/Ta₂O₅) switching oxide structures is illustrated in Figure 1. The switching oxide layers are deposited using thermal ALD (Veeco Fiji2 ALD), while the top and bottom contacts are formed using an Angstrom Engineering sputtering tool. The process begins with the growth of a 200 nm-thick SiO₂ layer on a Si substrate through thermal oxidation as shown in Figures 1a, b.

The substrate undergoes thorough cleaning in an ultrasonicator with acetone and isopropanol (IPA) for 10 min each to remove surface impurities, such as dust particles and organic residues. To pattern the bottom electrode (BE), direct-write photolithography is performed using a MicroWriter ML^® 3 Pro system (Durham Magneto Optics, DMO), followed by sputtering of a 50 nm TiN layer at room temperature, as shown in Figures 1c–f. The photolithography process utilizes a 5 µm resolution lens, a 405 nm light source, and a pre-optimized exposure dose of 180 mJ/cm² to accurately define all three levels of the mask design. Next, ∼8 nm HfO₂ and ∼2 nm Ta₂O₅ layers are deposited as a switching oxide layer without breaking vacuum, as illustrated in Figure 1g. The deposition temperature for both materials is maintained at 300°C. HfO₂ is deposited using tetrakis (dimethylamido) hafnium (IV) (TDMAHf) as the hafnium precursor and H₂O as the co-reactant, requiring nearly 78 ALD cycles. For Ta₂O₅, pentakis (dimethylamido) tantalum (PDMATa) serves as the tantalum precursor with H₂O as the co-reactant, necessitating around 25 ALD cycles to achieve a ∼2 nm thickness.

The precursor bottles are heated to 75°C for TDMAHf and 105°C for PDMATa. Each HfO₂ ALD cycle involves a 0.25 s TDMAHf pulse followed by a 5 s Ar purge, and a 0.06 s H₂O pulse followed by another 5 s Ar purge, resulting in an average growth per cycle (GPC) of 0.1028 nm. For Ta₂O₅ deposition, each ALD cycle consists of a 0.6 s PDMATa pulse, a 5 s Ar purge, a 0.06 s H₂O pulse, and a final 5 s Ar purge, achieving an average GPC of 0.0842 nm. After depositing the oxide layers, reactive ion etching (RIE) with CHF₃/Ar plasma is used to expose the contact pads for the BEs. The etching duration is approximately 13 min to etch the HfO₂/Ta₂O₅ bilayer, with an etch rate of 0.820 nm/min (Figures 1h–j). Finally, photolithography is performed to pattern the 50 nm top TiN electrode (TE) (Figures 1k–m). Figures 1n, o and (o) illustrate the optical microscope images of the final device on a large-area wafer scale having a device structure of TiN/HfO₂/Ta₂O₅/TiN. The memory cell size in the fabricated arrays is (10 × 10) µm².

We utilize a custom in-house memristor testing tool (ArC ONE) for conducting these electrical measurements. Figure 2 illustrates the primary resistive switching mechanism observed in the fabricated bilayer memristive devices. The conduction process in these bilayer structures is primarily linked to the formation of conductive paths composed of oxygen vacancies (Ryu et al., 2021). Figure 2a shows the pristine device state in which there is no electric potential applied over the device. Typically, oxygen vacancies in resistive switching oxides are generated during the electroforming process, as shown in Figures 2b, c. The creation of conductive filaments during this initial forming stage can be explained by the migration of oxygen vacancies or ions from the TE toward the BE. Figure 2d shows the electroforming process during current-voltage (I-V) measurements wherein forming voltage (V _F) is +5.5 V. Here, it should be noted that the initial resistance of the pristine device is in the range of 10–20 GΩ and after the forming event the device resistance is in the range of 5–7 kΩ.

Additionally, the fabricated devices demonstrate analog resistive switching behavior (Kumar et al., 2022b). To prevent permanent damage during measurements, a compliance current (I _CC) of 1 mA is applied to the device (Kumar et al., 2023). After the forming event, ±4.5 V is imposed over the TE of the fabricated devices while BE is kept at the ground.

As observed from Figure 3a, under the positive voltage from 0 to +4.5 V, the memristive device is switched from a high resistance state (HRS) to a low resistance state (LRS) at the voltage of +3.75 V (i.e., D1), and this event is termed as “SET” process. While, under the negative voltage bias from 0 to −4.5 V on TE, the device resistance state is switched back from LRS to HRS at the voltage of −4.01 V (i.e., D1), and this process is known as the “RESET” process. Figures 3a–5a(D1-D34) depict the analog-type resistive switching responses of the randomly selected memristive devices from the fabricated crossbar array architecture. As observed, these devices exhibit stable bipolar resistive switching characteristics with some variations in the device switching voltages (V _SET and V _RESET) as illustrated in Figures 5b, 6a, b, e, f. Figure 5b displays the average values of the first 10 switching cycles of V _SET and V _RESET of individual devices (D1-D34).

However, some observable variations have been seen which might have appeared due to the crossbar array configuration wherein sneak-path current is a serious concern (Shi et al., 2020; Chen et al., 2021). As discussed, the fabricated devices essentially required an electroforming process to obtain the switching responses. Therefore, non-uniform heat dissipation can cause localized hot spots. These variations can lead to either abrupt or gradual switching depending on the temperature dependence of the underlying mechanisms (Kumar et al., 2022c). Additionally, in memristive devices, switching involves the formation and rupture of conductive filaments (CFs) composed of defects including oxygen vacancies. The stochastic nature of CF formation leads to variability: abrupt switching occurs when a filament forms or breaks suddenly, while gradual switching results from partial or progressive filament changes. This inherent randomness contributes to inconsistencies in device behavior (Kumar et al., 2022c). Additionally, long endurance was also performed which further confirms the better device stability as shown in Figure 5c. However, each device has inherent variations (or uncontrolled ionic motion during the switching process) in the ON/OFF ratio, which might lead to the overall variation in the LRS and HRS values throughout the different devices over the wafer scale. Moreover, in the fabricated devices, a thin layer of Ta₂O₅ acts as the thermal enhanced layer to improve the uniformity of oxygen vacancy distribution during the switching process (Xiang et al., 2019; Wanga et al., 2021).

As analyzed in Figure 6, the randomly selected memristive devices show nearly 22.72% variations in the V _SET concerning maximum V _SET voltage as shown in Figure 6a while 15.72% variations in the V _RESET concerning maximum V _RESET voltage of the device as shown in Figure 6e. These observed variations cover a large area of the wafer as different locations of the device have been considered and electrically characterized to perform statistical analysis. Additionally, these variations are also correlated with the anomalies in the device fabrication process, material growth conditions, and quality of deposited thin films (Zheng et al., 2024; Li et al., 2021).

Moreover, time series analysis (TSA) techniques are utilized to model and forecast variations in the switching voltages, specifically V _SET and V _RESET. This statistical framework significantly helps to analyze collected data at regular intervals and predict the inherent patterns and trends in datasets (Roldan et al., 2021; Alonso et al., 2021; Roldan et al., 2023). This analytical methodology supports precise modeling, prediction, and forecasting and has been extensively applied across diverse research disciplines.

In recent years, the application of TSA to investigate and predict variations in switching parameters within resistive switching devices has garnered significant attention and exhibited substantial growth (Alonso et al., 2021; Thorat et al., 2024; Mullani et al., 2023). In this study, the analysis is focused on the V _SET and V _RESET series. Given the stoichiometric complexities and variability intrinsic to the switching parameters of memristive devices, addressing their nonlinear behavior necessitated the adoption of advanced TSA methodologies. To this end, the Holt-Winters Exponential Smoothing (HWES) technique is employed to model, predict, and forecast the data series as reported in (Rokade et al., 2024; Katkar et al., 2022).

The derived parameters α, β, and γ estimates are instrumental in constructing predictive models for V _SET and V _RESET. For V _SET, the respective values are 1.4901 × 10⁻⁸, 1.4894 × 10⁻⁸, and 3.0798 × 10⁻¹⁵, while for V _RESET, these are 1.49 × 10⁻⁸,1.489 × 10⁻⁸, and 6.1825 × 10⁻¹⁷. Utilizing these parameters, predictions for the switching voltages are generated, with the results illustrated in Figures 6b, f. Notably, the TSA approach proved highly effective in forecasting the switching voltages V _SET and V _RESET for the next 30 devices, as depicted in Figures 6b, f. These predictions closely aligned with the experimentally obtained values, thereby demonstrating the predictive accuracy of the HWES technique. The outcomes further reveal that the HWES method successfully captured variations in both switching voltages and current states. These findings validate the reliability of HWES in modelling the switching parameters of HfO₂/Ta₂O₅-based devices. Furthermore, the autocorrelation function (ACF) and partial autocorrelation function (PACF) values of the residuals for all series, are presented in Figures 6c, d and Figures 6g–h, indicate an absence of significant lag in the residuals. This lack of correlation in both ACF and PACF confirms the robustness of the model (Rokade et al., 2024; Khot et al., 2024).

The realization of high-k dielectric metal oxide-based memristive devices faces a significant challenge in the fluctuations in device switching parameters during device-to-device (D2D) and cycle-to-cycle (C2C) (Kumar et al., 2022b; Baeumer et al., 2017; Sangwan et al., 2018). In the case of D2D, the variations are introduced due to inhomogeneity and anomalies in fabrication processes including nonuniformity and smoothness in the deposited thin films while C2C variations are dominated due to the stochastic nature of the resistive switching process (Sangwan et al., 2018). Therefore, to better analyze and quantify these fluctuations, the coefficient of variation (C _V) plays a pivotal role which is defined as the ratio of the standard deviation (σ) to the mean (μ) (Chen et al., 2020; Kumar et al., 2022b). This crucial metric provides insights into the consistency and reliability of switching parameters.

In our study, device switching voltages (V _SET and V _RESET) of randomly selected devices are utilized and for C2C C _V, a single memristive cell is considered. This approach allows us to gauge the extent of variability and enhance device performance evaluation. The cumulative distribution function (CDF) of V _SET and V _RESET in D2D and C2C are illustrated in Figures 7a–d which is calculated by using Equation 1 as follows for each value of V _SET and V _RESET. C D F x = 1 2 1 + erf x − μ σ 2 (1)

Here, µ is the mean, σ is the standard deviation, and x is the input value. To evaluate the values of D2D C _V, randomly selected 34 devices and for C2C C _V, 50 consistent cycles were utilized. As observed from Figure 7a, the values of D2D C _V in V _SET and V _RESET are presented wherein V _SET C _V and V _RESET C _V are 6.09% and 3.22%, respectively. These lowest C _V values in switching parameters are further associated with the thin film uniformity and low leakage current in the fabricated devices (Yun et al., 2021; Park et al., 2024). Figures 7b–d shows the values of C2C C _V in multiple devices (D1, D5, and D8). Here, values of C2C C _V are 1.76% (V _SET), 2.26% (V _RESET), 2.28% (V _SET), 3.58% (V _RESET), and 4.16% (V _SET), and 2.14% (V _RESET) associated with the device D1, D5 and D8, respectively. Moreover, these minimal values of C _V validate the stability and reproducibility of the fabricated devices. Furthermore, the lower C2C variations ensure the reliability and stability consistency in memory cells across multiple read/write cycles. Additionally, low C2C variations support precise control over the resistance levels, which enables more accurate synaptic weight tuning in synaptic and neuromorphic computing tasks (Sun and Yu, 2019). The precise tunability of the synaptic weight in the biological synapses further enhances learning and recognition tasks.

The potentiation and depression functionality of the artificial synapse has been implemented by applying the input voltage pulses. Figure 8a shows the potentiation (P) process, wherein the device conductance is continuously strengthened under the application of a train of 50 positive successive pulses with V _A = +4.0 V, PW = 100 µs, and PD = 10 µs In the case of the depression (D) process, the device conductance is continuously weakened under the application of a train of 50 negative pulses with V _A = −4.0 V, PW = 100 µs, and PD = 10 µs Here, the amplitude of the read voltage pulse (V _R) is ±0.5 V, as depicted in Figure 8c. Figure 8b depicts the combined plot of potentiation and depression which assists in evaluating the value of the nonlinearity (NL) factor for P and D processes and the calculated value to be 0.43 at pulse number (n) = 25. Here, to evaluate the value of the NL factor, Equation 2 formulation has been utilized (Kumar et al., 2022a; Wang et al., 2016): N L   F a c t o r = Max G P n − G D n  for  n = 1  to  N (2) where, G _P(n) and G _D(n) are the conductance values after the nth P-pulse and nth D-pulse, respectively. Here, it should be noted that the evaluated value of the NL factor is normalized with overall plasticity and defined in the range from 0 to 1 during a synaptic weight update sequence comprising an equal number (N) of consecutive P-pulses and D-pulses. However, for a completely linear synaptic weight update, the value of the NL factor is equal to 0 (Wang et al., 2016) wherein learning and forgetting processes can be overlapped. The obtained memristive device characteristics show a similar agreement with the P and D functionalities of the real biological synapse (Zhao et al., 2022). Moreover, paired-pulse facilitation (PPF) defines the pivotal information in short-term plasticity (STP) behavior (Santschi and Stanton, 2003), showing how the synaptic response of the first stimulus enhances the synaptic response to the second stimulus. In the biological synapses, PPF behavior is defined by the amplification of the second post-synaptic response current under the applications of two consecutive spike stimuli, where the interval between spikes is shorter than the recovery time (Zhang et al., 2017). Figure 8d shows the experimental characterization of PPF functionality in the fabricated devices which is calculated by utilizing Equation 3. This experimental evidence underscores the device’s capability to replicate crucial aspects of PPF behavior which is also observed in the biological synapses, showcasing its potential to emulate synaptic plasticity in neuromorphic computing (Tang et al., 2022). P P F = A 2 − A 1 A 1 × 100 % (3) here, A _1, and A ₂ represent the amplitude of currents corresponding to the first and second voltage stimulus, respectively. In Figure 8d, the interrelation between the increase in rate and the amplitude of the synaptic response current during successive positive or negative pulses is illustrated for different time intervals. The pulse interval is systematically varied from 5 µs to 50 µs up to 200 µs, while maintaining a fixed pulse magnitude and width of 4 V and 10 µs, respectively. From Figure 8d, it is observed that under the consistently positive paired-pulse facilitation (PPF) across all pulse intervals, indicating that the current during the second pulse consistently exceeds that of the first pulse. In the case of paired-pulse depression (PPD), the current in the second pulse consistently decreases behind that of the first pulse as depicted in Figure 8e. Therefore, this electrical investigation provides in-depth insights into the dynamic behavior of the device, and its ability to replicate PPF and PPD mechanisms as similarly observed in the real biological synapses while varying pulse intervals. Finally, Table 1 shows a detailed comparison analysis between our work and other reported literature (Ghenzi et al., 2024; Ryu et al., 2021; Napari et al., 2024; Kumar et al., 2025; Kim et al., 2018).

Herein, we have reported the microfabrication process and in-depth electrical characterizations of the bilayer (HfO₂/Ta₂O₅) memristive devices. A low-temperature single thermal ALD tool is utilized to deposit both active oxide layers at 300°C without breaking the system vacuum to minimize the effect of surface anomalies. The fabricated memristive devices required an electroforming process to show the stable bipolar resistive switching responses. The obtained outcomes suggest that all devices depict stable switching responses over hundreds of cycles. The randomly selected devices from wafer-scale memristive arrays exhibited 22.75% (V _SET) and 15.72% (V _RESET) variations in the device switching voltages corresponding to the maximum switching voltage of the tested devices. Additionally, the adopted TSA analysis efficiently predicted the device switching voltages (V _SET and V _RESET) for the next 30 devices which was well matched with the obtained experimental data. The values of coefficient of variability (C _V) for D2D (C _V: 3.22%) and C2C (C _V: 1.76%) revealed the remarkable stability and reproducibility of the fabricated devices and confirmed that the ALD-grown thin film has a smooth and uniform surface. Furthermore, the fabricated devices are efficiently able to mimic the synaptic functionalities including potentiation, depression, PPF, and PPD under low pulse width which makes them a perfect candidate for synaptic and neuromorphic devices. The value of the NL factor (0.43) is close to the ideal value which suggests that these device configurations can be useful for developing ideal synaptic systems.