Digital in-memory stochastic computing architecture for vector-matrix multiplication - Agwa, Shady; Prodromakis, Themis (Frontiers in Nanotechnology, 2023)
The applications of the Artificial Intelligence are currently dominating the technology space; meanwhile, the conventional Von Neumann architectures are struggling with the data-movement bottleneck to meet the ever-increasing performance demands of these data-centric applications. The major bottleneck of these applications is the vector-matrix multiplication cost in the binary domain. This paper presents a new digital in-memory stochastic computing architecture that utilizes the simplicity of the stochastic computing to do in-memory vector-matrix multiplication. The new proposed architecture profits from different new approaches including: new stochastic number generator with ideal binary-to-stochastic mapping, accurate-enough low stochastic bit-precisions due to best seeding, hybrid stochastic-binary accumulation for vector-matrix multiplication, and converting conventional memory read operations into on-the-fly stochastic multiplication operations. Thanks to the combination of these approaches, the accuracy analysis of the vector-matrix multiplication benchmark shows that scaling down the stochastic bit-precision from 16-bit to 4-bit achieves nearly the same average error (less than 3%). The extracted analytical model of the proposed in-memory stochastic computing architecture shows that the stochastic 4-bit architecture achieves the best throughput per sub-array (122 Ops/Cycle), which is 4.36x better than the 16-bit stochastic precision, while maintaining a small average error (2.25%).