For artificial intelligence (AI) applications, traditional computer hardware based on the serial von Neumann architecture suffers from a major performance and energy-efficiency problem, mainly due to the massive data transfer between processing and memory units. One promising way to overcome this so-called von Neumann bottleneck is to embrace computational neuroscience and neuromorphic engineering paradigms to create parallelized spike-based computing systems (Yang et al., 2020). In that scope, emerging two-terminal resistive memories (i.e., memristors) are considered as key building blocks, owing to their controllable conductance state which can be used to encode synaptic weights (Li and Ang, 2021). The main synaptic-like behaviors reported to date include short- and long-term memory (STM/LTM), paired-pulse facilitation (PPF) and depression (PPD), spike-timing-dependent plasticity (STDP), spike-rate-dependent plasticity (SRDP) and metaplasticity (Zhu et al., 2020).

The two-terminal architecture of typical memristive devices can only authorize the emulation of homosynaptic plasticity–input-specific changes at synapses directly involved in a pre-synaptic activation. Hence, most of the studies done on memristor-based spiking neural networks (SNN) rely solely on Hebbian-type learning rules (e.g., STDP) based on homosynaptic plasticity (Chua et al., 2019). Such SNNs are prone to weight saturation (i.e., runaway dynamics) and are devoid of synaptic competition, which can weaken network representativity due to overexcitability or silencing of neurons (Moser and Moser, 1999; Chen et al., 2013). These phenomena are usually at the source of poor learning and computing performance. Recent advances in neuroscience have demonstrated that synaptic plasticity in biological neural networks is regulated not only by homosynaptic plasticity, but also by synaptic interactions (competition, cooperation) and more importantly heterosynaptic plasticity–modulatory input-dependent changes at inactive synapses related to strong post-synaptic activities (Bailey et al., 2000; Chistiakova et al., 2014). These complex heterosynaptic behaviors, which can be mediated by limited available energy and modulatory cells (e.g., astrocyte and interneurons, see Figure 1A), play an important role in the stabilisation and memory functions of neural systems. They are indeed responsible for the normalization of all synaptic weights connected to a neuron, meaning that the total weight remains constant. Such regulation mechanisms strongly limit the risk of synaptic weights to saturate, and thus contribute to improve the learning capability and computing performance of the network. Therefore, it appears that homosynaptic and heterosynaptic plasticity mechanisms have complementary computational properties at different spatiotemporal scales that could be beneficial for neuromorphic systems.

In recent years, the use of heterosynaptic plasticity in software SNNs has resulted in improved learning capabilities (Susi et al., 2018; Daram et al., 2020). The implementation of an astrocyte-reinforced STDP has also been reported in Intel’s Loihi neuromorphic chip (Tang et al., 2019). Going forward, improving the online learning capabilities, the speed and the energy efficiency of future bio-inspired computing systems will require novel neuromorphic hardware that natively emulate both homo- and heterosynaptic plasticity mechanisms. For this reason, multi-terminal memristive devices have attracted a lot of attention lately due to their tunable and rich resistive switching dynamics at various time scales, enabled by the interplay of local modulatory voltage signals and complex nanostructures based on emerging materials. Indeed, outside from the two terminals that are required to perform resistive switching, the additional terminals can be used as gates to control the electric field across the switching materials, resulting in a modulation of the switching dynamics similar to heterosynaptic plasticity. This feature opens new opportunities to implement in hardware desirable advanced bio-inspired learning rules and global regulation mechanisms. Moreover, additional terminals can also be used as active electrodes allowing to decouple the reading and programing processes, otherwise impossible with 2-terminal devices. This mechanism combined with gate tuning could offer better control over the switching linearity and symmetry, recently identified as key factors in efficient neuromorphic hardware (Burr et al., 2015; Xiao et al., 2020). Using multiple active electrodes also provides the possibility to go beyond the single synaptic element by implementing in a single device multiple artificial synapses capable to interact with each other. Finally, multi-terminal devices enable to engineer multiple input/output components, thus increasing the fan-in/fan-out at the device level without requiring complex interconnections or circuit overhead. As depicted in Figures 1B,C, both vertical and planar multi-terminal architectures are currently investigated with the goal to mimic complex plasticity mechanisms such as heterosynaptic plasticity and synaptic interactions between multiple electrodes.

In this mini-review, our aim is to provide a brief overview of the latest progress in multi-terminal memristive devices paving the way for the hardware implementation of both homo- and heterosynaptic plasticity. We will focus our analysis of the reported studies in the light of their compatibility with industrial complementary metal oxide semiconductor (CMOS) technologies. The compatibility of multi-terminal memristive devices with the semiconductor industry is indeed of major importance for future endeavors aiming to develop truly scalable low-power high-performance neuromorphic systems. As such, this article specifically targets inorganic solid-state memristive devices fabricated on silicon substrate having the potential to be co-integrated with CMOS circuits. This article will first outline multi-terminal devices with a vertical architecture, before reviewing planar devices. For both sub-sections, reported works include memristors and memtransistors based on metal oxides, nanoparticles, nanowires, 2D materials and heterostructures. The last part of this article will discuss future research opportunities and development directions aiming to tackle challenges related to CMOS-compatible fabrication, device performance and scalability.

This section reviews the state-of-the-art of vertical and planar memristive devices with three or more terminals enabling tunable synaptic plasticity and synaptic interactions. As shown in Figures 1B,C, devices are classified as vertical (planar) when the switching mechanisms and the electronic current are perpendicular (parallel) to the substrate. All devices reviewed are summarized in Table 1.

The growing necessity to implement advanced synaptic functions in neuromorphic hardware has pushed several groups to explore novel multi-terminal memristive devices based on metal oxides, nanoparticles, nanowires and 2D materials. Rich and tunable synaptic-like behaviors have been demonstrated, including short- and long-term heterosynaptic plasticity as well as synaptic interactions. Lately, 2D materials such as graphene, SnSe, MoS₂, WSe₂, GaSe and In₂Se₃ have emerged as promising candidates owing to their atomic-level thickness and tunable electronic properties that offer lower energy consumption and improved synaptic emulation. Although these demonstrations contribute to bridging the gap between software and hardware in the field of neuromorphic engineering, major challenges remain in terms of materials, device operation conditions, design and integration with CMOS technologies.

Materials and scalable fabrication processes compatible with CMOS technologies have to be investigated. Outside from memristive devices based on oxide thin films (Yang et al., 2017; Nagata et al., 2019), most demonstrations involve 2D materials which rely on fabrication processes that are not scalable such as exfoliation process (Yang et al., 2019; Zhu et al., 2019) or patterning with focused ion beam (Jadwiszczak et al., 2019). Some works employed wafer-level chemical vapor deposition (CVD), but the required thermal treatment is way above 400°C (Sangwan et al., 2018a; Wang L. et al., 2019; Zhao et al., 2020) which makes this approach still incompatible with CMOS processes. Ideally, developing industrial-grade deposition processes of 2D materials should result in well controlled atomically thin layers of perfectly arranged structures at the wafer level. This should lead to a significant reduction of cycle-to-cycle and device-to-device variability problems, which are still not solved in the case of conventional oxide-based memristive materials prone to defects and contaminant issues. Another important aspect of current studies is the overabundant use of Au and Pt as electrodes. The use of inert materials readily available in semiconductor foundries (e.g., TiN, W) should be investigated, as well as their impact on resistive switching mechanisms.

Regarding switching operations, reported devices relying on a back gate to modulate the switching operations necessitate gate voltage in the range of tens of volts. Planar devices based on 2D materials can also exhibit very high switching voltages, with values ranging from 20 to 80 V (see Table 1). For tunable memristive devices to be co-integrated with CMOS technologies, breakthroughs in fabrication and materials engineering remain to be made for the operation conditions to be in the range of a few volts. For example, as shown in some studies (Yang et al., 2017; Sangwan et al., 2018b), the integration of the modulation electrode as a top/side gate instead of a back gate can reduce the required voltage by an order of magnitude. Advanced designs such as gate-all-around architecture could potentially improve further the control on synaptic modulation.

In terms of scalable integration, one important milestone is to achieve the integration of synaptic devices into a fully connected network. In that aspect, further work has to be done to convert current planar devices into vertical multi-terminal memories. The vertical architecture indeed allows the fabrication of crosspoint structures, which provide the highest integration density when interconnected into a crossbar array. Furthermore, vertical integration opens new perspectives for monolithic 3D integration. In fact, conventional 2D integration requires complex interconnection layouts to mimic the parallel structure of the brain. Integrating multiple input/output at the device level and taking advantage of 3D interconnects with both lateral and vertical access lines (Xue et al., 2021) could help relaxing the important limitation of todays hardware for neuromorphic engineering. To this day, only one group has reported the fabrication of crossbar arrays of vertical multi-terminal memories using a combination of SiO thin film and graphene as electrode (Choi et al., 2021). However, some concerns exist regarding the compatibility of emerging memristive materials with high-density integrations. On the one hand, conventional memristive thin films are well suited for a vertical integration owing to their isotropic resistive switching mechanisms and improved performance at lower scale. On the other hand, 2D materials exhibit anisotropic memristive properties, resulting in different behaviors between in-plane (planar integration) or out-of-plane (vertical integration) resistive switching. Furthermore, a vertical integration could prevent the use of photonic or optoelectronic properties for resistive switching or modulation methods. These aspects should therefore be taken into account when determining the type of integration for a specific application using a certain type of 2D material. In that scope, innovative high-density integration schemes should be investigated for 2D materials. For example, a 3D integration taking inspiration from vertical random-access memories (VRAM) and the work of (Herrmann et al., 2018) demonstrating a vertical switching junction driven by two planar electrodes could result in promising stackable architectures.

Some groups have started to investigate the benefits of gate-tunable plasticity in neural network simulations, reporting the ability to optimise the learning rate and improve MNIST classification accuracy (Yang et al., 2017; He C. et al., 2020). There are now opportunities to explore even more interesting applications of multi-terminal devices for neural networks based on either formal or spiking neurons. The use of modulation gates or additional active terminals could indeed be investigated to develop novel modulated local learning rules and weights regulation mechanisms. In the meantime, major hardware-related problems like switching linearity/symmetry, device-to-device variability and impedance mismatch have to be mitigated before large-scale memristive neuromorphic circuits can be developed. In that scope, the results of several studies in this review suggest that the tuning of both the switching dynamics and the resistance range can contribute to solve these problems. Ideally, both switching non-idealities and impedance mismatch could be dynamically minimized using smart programing/reading feedback loops taking advantage of the tunable dynamics of the devices. This approach could bring more flexibility to circuit design, relaxing constrains on hardware parameters for easier mix-and-match combinations of synaptic and neuron circuit blocks. However, the complexity and energy cost of an additional control circuit could be detrimental and should be investigated.

In the context of brain-inspired computing based on spiking neural networks, the use of multi-terminal devices is clearly advantageous for the implementation of complex behaviors such as synaptic cooperation/competition and weight normalization. Indeed, integrating all the network-level interdependence learning rules with standard 2-terminal would necessitate complex peripheral circuits and memory modules to keep track of all the weights, compute the new weights and update all memristive synapses. This would induce scalability, energy consumption and delay issues. On the other hand, devices with multiple active electrodes on the same memristive material can natively implement rich interactions between multiple synapses in a single device, removing the need for additional peripheral circuits. Only a few studies have been able to achieve such advanced behavior using Li-doped 2D materials, and network-level weight normalization has yet to be demonstrated. Nevertheless, these advances are promising and should be explored further in the future.

Going further, efforts should be focused on studying the hardware implementation of heterosynaptic plasticity at the network level, as well as software-hardware co-design aiming towards weight normalization or heterosynaptic metaplasticity (Hulme et al., 2014). Only hardware-based demonstrations at the network level will allow to evaluate if these novel learning capabilities enabled by advanced memristive devices are worth potential increases in energy consumption, circuit area or design requirements in neuromorphic systems. The answer is not clear at this point, and in-depth network-level simulations and hardware demonstrations could reveal that the advantages of multi-terminal memristive devices are outweighed by drawbacks such as increased footprint, more complex routing and additional voltage sources. Additionally, there is still no guaranty that pushing further in the direction of bio-plausibility will result in optimal performance compared to highly parallelized and high-speed standard electronics. However, in the case where the benefits of the multi-terminal devices are clearly established, academia and industry should work together on improving their technological maturity and overall performance.