The slot waveguide structure was first proposed by Almeida et al. (2004) as a simple way to achieve extremely strong optical confinement in a low refractive index medium. Typically, an all-dielectric slot waveguide is formed by two high index waveguiding regions (e.g., silicon) separated by a narrow region of low index material (e.g., air, silica or polymer). Due to the discontinuity in the electric field at the high index contrast interfaces, such a structure supports an optical mode which can confine and guide light along the nanometer-size region of low index material, as shown in Figure 1. This unique property of slot waveguides has been exploited in many areas such as sensing (Barrios et al., 2007; Carlborg et al., 2010), non-linear optics (Muellner et al., 2009; Martínez et al., 2010), electro-optic modulation (Baehr-Jones et al., 2008; Chen et al., 2009; Koos et al., 2009), light sources (Guo et al., 2012; Tengattini et al., 2013), etc. However, a major limitation of slot waveguides is their high propagation loss. Since the light is more confined in the slot region, any surface roughness, introduced during the fabrication process, causes significant scattering loss. Therefore, fabrication of low-loss slot waveguides is challenging and the lowest reported propagation loss was 10 dB/cm (Baehr-Jones et al., 2005), from a standard vertical slot waveguide. There are different approaches proposed in the literature to reduce this propagation loss. For example, strip-loaded slot waveguides have been proposed with improved propagation loss of 6.5 dB/cm (Ding et al., 2010); albeit for a reduced mode confinement in the slot region. Spott et al. (2011) reported a record low propagation loss of 1.7 dB/cm from a slot waveguide by introducing different silicon arm widths. This geometry also compromises the mode confinement in the slot region due the asymmetry in the waveguide geometry. Alasaarela et al. (2011) adopted a different approach to reduce the propagation loss by coating the waveguide surface by a thin layer of titanium dioxide. This layer with intermediate refractive index effectively reduces the optical field intensity at the high index contrast interface, and they reported a propagation loss of 7 dB/cm for a slot waveguide.

In this letter, we present a new and simple method of reducing waveguide loss by surface smoothening using a combination of dry and anisotropic wet etching processes. The wet etching process was used to smoothen the residual side wall roughness after dry etching. Here, we used an aqueous solution of tetramethylammonium hydroxide (TMAH), which is widely used for anisotropic wet etching of silicon. Due to its strong alkalinity, TMAH reacts very differently with silicon depending on the crystallographic orientation of the exposed region. For example, while (100) and (110) planes are etched by a TMAH solution, (111) plane remains almost unaffected. Since this is a completely chemical process and strongly depends on the crystallographic orientation of the etched surface, ideally we should expect an ultra-smooth surface with atomic level irregularity. Previously sub-dB propagation loss in silicon strip waveguides has been demonstrated using TMAH-based wet etching process (Lee et al., 2001; Debnath et al., 2016). In this work, by combining dry and wet etching processes, we managed to reduce the propagation loss of a slot waveguide with 200-nm slot width from 10.5 to 3.7 dB/cm and for a strip waveguide from 2.7 to 1 dB/cm.

The fabrication process flow is shown in Figure 2. The slot waveguides were fabricated on two silicon-on-insulator (SOI) substrates, namely sample A and sample B. Both the SOI substrates had 220 nm thick layers of Si with (110) surface orientation on 2 μm thick buried oxide (BOx). The advantage of choosing the (110)-oriented substrate lies in the fact that (111) planes are normal to the (110) surface along (112) direction. As a result, when the waveguides are designed along the (112) directions, the (111) planes will act as an etch stop during the smoothening process. During the fabrication process, first a 20-nm thick layer of SiO₂ was thermally grown by annealing the SOI substrates at 1000°C in O₂ (dry anneal) for 6 min in a quartz furnace tube. The substrates were then spin coated with a 250-nm thick ZEP-520A positive e-beam resist layer. Using e-beam lithography, the desired waveguide patterns were exposed onto the ZEP layer via a 5-nm spot size. The waveguides were designed to align along the (11-2) direction on the SOI substrates. After developing the exposed resist layer, the waveguide patterns were transferred to the SiO₂ hard mask and subsequently to the SOI layer in an inductively coupled plasma (ICP) etcher using a SF₆/C₄F₈ chemistry. After the dry etching process, the remaining resist was removed in an O₂ plasma asher. Final cleaning was carried out in fuming nitric acid and then diluted hydrofluoric acid. Surface roughness smoothening using anisotropic wet etching was carried out only on sample B. To avoid the formation of any native oxide layer, immediately after the HF cleaning process, the substrate was immersed in a 25% aqueous solution of TMAH at room temperature for 10 min. This duration was sufficient to significantly reduce the roughness from the waveguide surfaces. During this wet etching process, the top surfaces of the waveguides were protected by the SiO₂ hard mask while any roughness on the waveguide side walls was reduced. Since the etch rate is very slow along the (111) direction, we expect an atomically flat and vertical side walls after the wet etching process. For comparison, the wet-etching step was omitted for sample A. Figures 3A,B show the SEM images of the slot waveguides without (sample A) and with (sample B) roughness smoothening using TMAH wet etching, respectively. From the images, it is obvious that the surface roughness has been significantly reduced after the wet etching process. We have further carried out a detailed sidewall roughness analysis using atomic force microscopy (AFM). We have used a special tapered AFM tip from Bruker (CDF100) to easily access the vertical side walls of the waveguides. The AFM image was then processed using Gwyddion AFM analysis software to extract the surface roughness information of the sidewalls. In the Figures 3C,D, the y-axis is along the length and the x-axis is along the height of the waveguide, whereas the surface roughness is represented along z-axis. The AFM images clearly reveals that the roughness reduces from an rms value of 6.7 nm (Figure 3C) for the dry etched waveguide to 1.4 nm (Figure 3D) for the wet etched waveguide. It is also important to note here that the slot waveguides which had undergone the wet etching step had 20 nm larger slot width than designed, due to the slow etching of (111) plane. This slow etching of the (111) plane can also be used to precisely control the slot width by simply optimizing the wet etching time. Although, in this work, we have used e-beam lithography due to its quick turned around time, the same wet etching process can be used to smoothen the waveguide surfaces realized using standard photolithography processes. Finally, another thermal oxidation was carried on both the substrates to grow a 5-nm thick layer of SiO₂, which acts as a surface passivation layer. In most applications, the slot waveguides are cladded with low index materials, such as polymers (Koos et al., 2009) or silica (Martínez et al., 2010). Here, we spin coated the substrate with 500-nm thick spin-on glass (SOG; Fox-16, Dow Corning) and annealed at 400°C in N₂ environment for 4 h to cure the SOG. This acts as a low-loss cladding for the slot waveguides which has the refractive index of around 1.45, similar to silica.

To summarize, in this letter, we have proposed and demonstrated a simple fabrication technique to realize low-loss strip and slot waveguides on SOI platform. Here, we combined both dry and anisotropic wet etching processes to reduce propagation loss. The waveguides were first defined during the dry etching process and then the anisotropic wet etching process was used to remove any sidewall roughness. Using this fabrication technique, we realized a slot waveguide with a minimum propagation loss of 3.7 dB/cm for a slot width of 200 nm. There are several advantages of our proposed fabrication technique. First, without using any asymmetry or multilayer structures, the propagation loss can be reduced in a symmetric slot waveguide. Second, our surface smoothening technique can be applicable to patterns realized using standard photolithography. Finally the slow etching rate of the (111) plane can be used to precisely control the slot width.

Anisotropic wet etching is very selective to crystallographic orientation of silicon. Although, on the one hand, this allowed us to realize atomically flat surfaces and reduce propagation loss through silicon waveguides; due to its dependence on the crystallographic planes, our fabrication process restricts designing of nanophotonic components only along certain directions. This limitation can be avoided by adopting a hybrid fabrication process, where only certain components of the photonic integrated circuit, e.g., slot waveguide, undergoes the roughness smoothening process using anisotropic wet etching.

All data supporting this study are available upon request from the University of Southampton repository at http://dx.doi.org/10.5258/SOTON/397774.

KD and SS conceived the idea. KD performed the device design and simulation. KD and AK performed the fabrication. SB performed the SEM imaging. SO performed the AFM imaging. KD wrote the manuscript. All the authors were involved in the analysis of the results and revision of the manuscript.

The authors declare that the research was conducted in the absence of any commercial or financial relationships that could be construed as a potential conflict of interest.