The traditional repetitive controller structure is shown in Figure 4, where k _rc is the repetitive controller gain. Q(z) is a low-pass filter or a constant less than 1, taken as 0.95 in this paper, to achieve a good trade-off between system stability and tracking accuracy. Z ^-N is the N-cycle delay, N = f _s/f _N, where f _s is the sampling frequency and f _N is the fundamental frequency of the power grid. S(z) is a phase lead compensator used to compensate for the phase lag of the system. As shown in its structure diagram, the repetitive controller embeds a fundamental cycle delay element internally. By attenuating the error current signal before accumulation, it achieves zero steady-state error tracking of the AC signal, improving the steady-state accuracy of the system. Introducing this algorithm into the inner loop controller of the APF can significantly improve the system’s control performance and steady-state accuracy.

However, the introduction of periodic delay limits its transient response in the early stages of disturbances, with a typical response lag of about one fundamental cycle, and it is relatively sensitive to frequency shifts. In contrast, a proportional-repetitive controller with a parallel structure can adapt to a larger repetitive control gain, thus achieving a faster dynamic response. Meanwhile, PI control has a simple structure, sufficient phase margin, and faster transient response, but it suffers from steady-state error relative to the AC reference. Based on these complementarities, this paper adopts a PRC controller series PI controller, combining the advantages of the PI controller’s fast dynamic response and the repetitive controller’s high steady-state tracking accuracy through optimized design. The proposed PRC-PI series controller system structure is shown in Figure 5, where G _PIi (z) is the PI controller of the inner current loop, and G(z) is the equivalent model of the decoupled inverter.

First, the series PI controller is designed. Based on the system modeling of the inverter in Section 2, the equivalent model of the system after the series PI controller for current i _d is shown in Figure 6. Here, T _s = 1/f _s , f _s is the sampling frequency, k _pi and k _ii are the proportional and integral coefficients of the PI controller, respectively, T _pwm is the inertial time constant of the inverter (T _pwm = 0.5T _s ), and k _pwm is the PWM equivalent gain of the inverter (k _pwm = 1).

Define the variable τ _i to satisfy: τ i = k p i k i i = L c R c (5)

Based on this, by substituting Formula 5 into Figure 6, the current closed-loop transfer function of i _d can be further simplified to Figure 7.

According to Figure 7, the open-loop transfer function of the RC system is expressed as shown in Formula 6. G c o s = k p i R c τ i s 1.5 T s s + 1 = k p i / 1.5 T s R c τ i s s + 1 / 1.5 T s (6)

Its cutoff frequency can be obtained through calculation: ω n i = k p i 1.5 T s R c τ i (7)

According to Formula 7, the values of k _pi and k _ii can be calculated as follows: k pi = 1.5 T s R c τ i ω n 2 k ii = k pi τ i = 1.5 T s R c ω n 2 (8)

In order to enhance the system response speed, this paper defines ω _ni as 40 times the grid voltage angular frequency, so that the system can maintain a good response speed to harmonics of the 40th order and below. T _s = 100 μs, L _c = 1mH, R _c = 0.01Ω, and by substituting into Formula 8, it can get k _pi = 4.74 and k _ii = 47.37.

The core of the PRC controller shown in Figure 5 is the design of the phase lead compensator S(z). Based on the transfer function and filter design requirements, to compensate for harmonics below the 40th order, the current loop cutoff frequency is designed to be 2 kHz. To ensure system speed and avoid resonance peaks, and in accordance with the optimal control principle, the system damping ratio is chosen to be 0.707. Therefore, the transfer function of this second-order low-pass filter is: S s = 2 π × 2000 2 s 2 + 2 × 0.707 × 2 π × 2000 s + 2 π × 2000 2 (9)

Perform bilinear discretization on Formula 9, Formula 10 can be obtained: S z = z − 2 + 2 z − 1 + 1 1.282 z − 2 − 3.066 z − 1 + 5.784 (10)

Considering that both the compensator and the digital filter have a fundamental period delay, the gain k _rc of the repetitive controller is set to 3 to compensate for the phase lag in the control process. Based on the requirement for system stability, the proportional coefficient k _prc ranges from 0 to 2. Based on this design, the final expression for the closed-loop transfer function of the system is derived as shown in Formula 11. G P R C − P I z = k p r c + k r c + Q z Z − N S z 1 − Q z Z − N G P I i z G z 1 + k p r c + k r c + Q z Z − N S z 1 − Q z Z − N G P I i z G z (11)

Figure 8 shows a Bode plot comparison of the current control inner loop under the PI and PRC-PI strategies.

Figure 8 compares the frequency responses of the current inner loop under PI and PRC–PI strategies. The PI-only loop exhibits insufficient attenuation and increasing phase lag in the mid-to-high frequency region, which may reduce stability margin when high-frequency components are present. By introducing PRC in series with PI, the controller intentionally provides selective high gain at discrete harmonic frequencies (internal-model property) to enhance harmonic tracking/suppression, while the overall loop gain is designed to remain close to 0 dB below approximately 1 kHz. More importantly, the gain rolls off rapidly above 1 kHz, which mitigates the amplification of high-frequency noise and PWM switching ripple. Therefore, the ripple-like or “comb-like” characteristics observed in Figure 8 are inherent features of the PRC’s internal model designed to provide high gain at specific harmonic frequencies. They do not indicate a broadband resonance or instability of the physical plant.

To verify the stability of the proposed PRC-PI controller, the Nyquist plot is illustrated in Figure 9. The critical point (−1,j0) s marked with a red cross. It can be observed that even with parameter variations, the Nyquist trajectories do not encircle the (−1,j0) point, satisfying the Nyquist stability criterion. Furthermore, the trajectories are located far from the critical point, indicating high robustness and sufficient stability margins.

The design of the PLL directly affects the accuracy and speed of target harmonic current extraction, thus impacting the harmonic compensation performance of the APF. To achieve high-precision and high-sensitivity phase tracking, this section employs a decoupled double synchronous reference frame phase-locked loop (DDSRF-PLL), as shown in Figure 10. The unbalanced three-phase voltage is mapped to a ±ω rotating dual dq coordinate system by Clarke transformation and two sets of Park transformations (positive and negative sequence), respectively. A decoupling network eliminates cross-coupling of sequence components and 2ω oscillations, accurately extracting the fundamental positive-sequence voltage and outputting the phase θ and frequency ω.

To compare the DDSRF-PLL with the traditional synchronous reference frame phase-locked loop (SRF-PLL), a three-phase unbalanced voltage simulation was conducted in Simulink software using a working voltage of 380V. The results of the two methods are shown in Figure 11. Figure 11a shows that the angular frequency of the traditional SRF-PLL phase-locked loop fluctuates greatly near the grid angular frequency, failing to achieve proper frequency locking. Figure 11b shows that the DDSRF-PLL-based system can perfectly lock the phase and frequency of the grid voltage after t = 0.06 s.

To balance computational complexity and selective compensation, this paper employs harmonic component extraction based on a synchronous rotating coordinate system, as shown in Figure 12. After Clarke and dq transformations of the three-phase load currents i _la , i _lb , and i _lc , the fundamental component is represented as a DC component in the dq coordinate system, while its higher harmonics are represented as AC components in the same coordinate system. For a specific harmonic n (positive sequence + n, negative sequence -n), the corresponding component in the dq coordinate system becomes DC. Therefore, i _ld equals the sum of the fundamental i _dlb and harmonic i _dlh , and i _lq equals the sum of the fundamental i _qlb and harmonic i _qlh .

By removing the AC terms using a low-pass filter, the DC estimates of the fundamental and selected harmonics are obtained. Inverse transformations yield the harmonic/reactive power compensation commands i _laref , i _lbref , and i _lcref . The switching quantity S _cq determines whether reactive power components are compensated simultaneously.

When the APF is powered on, the initial voltage of the DC bus capacitor is approximately 0 due to the parallel discharge resistor. It is necessary to smoothly raise the bus voltage to the rated 700 V within the device limits. To suppress power-on surges and avoid over-voltage/over-current, this paper adopts a two-stage soft-start approach, as shown in Figure 17.

First, in the uncontrolled rectifier pre-charging stage, the bus is slowly charged through the uncontrolled rectifier, limiting the inrush current and dv/dt, allowing the capacitor voltage to rise steadily. Then, a dual closed-loop takeover stage is entered. When the bus voltage reaches 90%–95% of the reference value and the charging current is below the set threshold and remains stable for a certain period, the system switches to a closed-loop control system of “voltage outer loop +current inner loop” to enter normal operation. Throughout the process, over-voltage/under-voltage and charging current protection conditions are set. Any trigger will maintain the pre-charging state or exit to a safe state. This strategy can smoothly establish the bus voltage and effectively protect power devices without changing the main circuit topology, providing stable DC support for subsequent harmonic and reactive power compensation.

An FFT analysis is performed on the grid current before compensation using a HIOKI HI3390 to obtain power quality parameters such as voltage and current waveforms and the spectrum of phase A current. The results are shown in Figures 18, 19. Due to the influence of nonlinear loads, the grid-side current distortion was significant before compensation, with a phase A THD of 28.82%. The three-phase power factors are 0.9572, 0.9584, and 0.9587, respectively, indicating the presence of significant reactive and harmonic components, which need to be compensated by APF.

The experimental results using the PI control strategy are shown in Figures 20, 21. As can be seen from the A-phase grid current waveform in Figure 20, the compensated current still exhibits significant non-sinusoidal characteristics under this comparative operating condition: peak and trough clipping and flattening phenomena appear, and zero-crossing points are accompanied by spikes and high-frequency ripples, indicating that harmonics and reactive power components are not sufficiently suppressed. The harmonic analysis results in Figure 21 show that compared to the pre-compensation THD of 28.82%, the PI dual-loop control only reduces the THD to 11.68%, leaving a significant amount of low- and mid-order harmonics. Specifically, the 5th harmonic accounts for approximately 5.24%, the 7th approximately 2.90%, the 11th, 13th, 17th, and 19th harmonics for approximately 2%–3% respectively, and the 23rd and 25th harmonics remain above 3%, indicating that the PI dual-loop control is not very effective in suppressing high-order harmonics. In summary, under these experimental conditions, the PI dual-loop circuit can only achieve limited current shaping and reactive power correction, and its harmonic suppression depth is insufficient and its steady-state tracking accuracy is limited.

To overcome the issue of insufficient gain in the PI dual-loop at low and mid-harmonic frequencies, resulting in limited compensation depth, a PRC was further introduced and connected in series with the PI to form a PRC-PI inner loop for comparative experiments. After using the PRC-PI as the current inner loop, the load current, grid current, and APF output current results are shown in Figure 22 after the system reaches steady state. From top to bottom, these represent the A-phase load current (green), grid current (purple), and APF output current (blue). As can be seen from Figure 22, the load current exhibits a stepped, strongly nonlinear distortion, indicating that the load side contains a large amount of harmonic and reactive components. After the APF is activated, the grid current is significantly compensated to an approximately sinusoidal wave, with a smooth waveform and significantly reduced distortion, leaving only slight ripples near the peak value, indicating that the grid current is dominated by the 50 Hz fundamental active component. Simultaneously, the APF output current exhibits compensation characteristics corresponding to the load distortion components, containing many high-frequency pulsations and spikes, reflecting that the device is providing harmonic and reactive currents to the load.

The grid current after PRC-PI compensation was analyzed using HI3390. The voltage and current waveforms, THD and harmonic content of phase A current, and power quality parameters were recorded, as shown in Figures 23, 24. As observed in Figure 23, small high-frequency ripples appear around the current waveform. These components are mainly related to PWM switching ripple and measurement noise, which are outside the designed current-loop effective bandwidth (since the system loop gain attenuates rapidly/rolls off steeply beyond ∼1 kHz, effectively filtering out high-frequency noise). Since the proposed PRC–PI focuses on selective compensation of low-order harmonics, the effectiveness is evaluated by the harmonic spectrum/THD results in Figure 24, where the dominant low-/mid-order harmonics are significantly suppressed. In practical implementations, additional damping measures (e.g., virtual impedance/active damping) can be integrated if a stricter suppression of switching ripple is required; this is considered as future work. After the APF was put into PRC-PI control, the THD of the phase A grid current decreased from 28.83% before compensation to 4.02%. Compared with 11.68% in the PI dual-loop condition, the THD was further reduced. The results show that after introducing repetitive control, the gain and phase characteristics of the system at discrete low-order harmonic frequencies are enhanced, thereby improving the selective suppression capability and compensation accuracy of low-order harmonics. Taking the 5th, 7th, 11th, and 13th harmonics, which were relatively severe in the grid current before compensation, as examples, the harmonic distortion rates before compensation were 22.69%, 10.92%, 8.80%, and 5.95%, respectively, and the harmonic distortion rates after compensation were 2.23%, 0.88%, 0.77%, and 0.20%, respectively. The calculated harmonic suppression rates were 90.17%, 91.94%, 91.25%, and 96.64%, respectively, indicating that the PRC–PI strategy has a good suppression effect.

The sudden change in load is a common experimental method to test the dynamic and transient response capability of the APF system. The APF is first operated in steady state under a nonlinear load with a resistance of 100Ω. At a certain moment, a 250Ω resistor is connected in parallel across the load to make the overall resistance 71.4Ω. The changes in various waveforms and parameters are recorded using instruments.

In Figure 25, the dark blue straight line represents the voltage waveform of the capacitor, and the sine wave in the middle represents the change in the grid current. It can be seen that when the load changes abruptly, the DC-side capacitor voltage experiences a slight voltage drop, and after one fundamental cycle of 20 ms, it stabilizes at the operating voltage of 700V. At the same time, the three-phase grid current does not generate a significant inrush current, and after one fundamental cycle of 20 ms, it can relatively stably complete the harmonic and reactive power compensation functions.

Figure 26 shows the details of phase A, from top to bottom: load current, grid current, and inverter output current. It can be seen that after the step change occurs, the amplitude of the inverter output current increases synchronously with the load increase to provide additional active/reactive power compensation. The grid current remains approximately sinusoidal with small transient deviations and converges within about one fundamental cycle, indicating that the inner current loop and repetitive control can quickly complete current redistribution and tracking under load abrupt changes.