The key components of the closed-loop circuit of the converter valve include the damping and voltage-sharing circuit circuits, the thyristor control unit (TCU), thyristors, the valve control system, and optical fibers. These essential components can be categorized into three groups based on their physical layout: the first group comprises the internal thyristor level of the converter valve, which includes the thyristors, damping and voltage-sharing circuit circuits, and TCU; the second group consists of the optical fiber circuits, such as the triggering and feedback fibers; the third group refers to the valve control unit (VCU). The spatial structure of the converter valve within the valve hall is shown in Figure 1.

A thyristor-level circuit of a converter valve consists of multiple thyristors connected in series, and each thyristor level is required to withstand approximately the same voltage. To ensure uniform voltage distribution among thyristor levels, the damping circuit, voltage-sharing circuit, and power-tapping circuit of the converter valve play important roles. On the one hand, they help guarantee uniform voltage sharing among levels over all frequency components of DC surge waveforms; on the other hand, they mitigate the transient voltage and current stresses experienced by thyristors during turn-on triggering and recovery.

The electrical schematic of the thyristor-level converter-valve circuit is shown in Figure 2. The thyristor-level converter valve and its damping and voltage-sharing circuits comprise the damping circuit, the voltage-sharing circuit, the TCU, and the thyristors. Specifically, R₂, C₁, and C₂ form the damping circuit, which is a resistive–capacitive network. During the commutation-extinction process, the damping voltage may oscillate, thereby providing transient charging to the TCU. The charging time constant is approximately 100 μ s , ensuring that the TCU can obtain a reliable working power supply before valve triggering. The damping capacitor C₃ and the fast power-tapping resistor R₃ connected in series constitute a fast power-tapping circuit. R_dc1 and R_dc2 form the voltage-sharing circuit, which is a series-resistor network with a relatively large resistance and high accuracy. It can be used to measure the voltage across the thyristor terminals and to generate the input voltages for the IP (thyristor feedback pulse), PF (thyristor protective firing), and RP (recovery protection) logic; it also provides the steady-state operating power supply for the TCU.

At present, engineering sites commonly use a dedicated converter-valve test instrument provided by the manufacturer to perform comprehensive impedance testing on the damping and voltage-sharing circuits across the terminals of a valve thyristor level, in order to determine whether abnormalities such as short-circuit or open-circuit faults exist in the branch. This method does not require dismantling the damping and voltage-sharing components; instead, a multi-frequency sinusoidal voltage with a frequency range of 50–100 kHz is applied across both terminals of the thyristor-level circuit. The peak voltage and peak current at each frequency point are measured, and the comprehensive impedance at the corresponding frequency is calculated as shown in Equation 1 as follows: Z f i = U peak f i I peak f i (1) where Z f i is the comprehensive impedance obtained at the test frequency f i , and U peak f i and I peak f i are the measured peak voltage and peak current at that frequency, respectively. It should be noted that this instrument-dependent approach can only obtain the overall equivalent impedance of the thyristor-level damping and voltage-sharing circuits and thus provides only qualitative judgments. It is difficult to further resolve the specific parameters of individual components, and therefore an accurate evaluation of whether a component meets specifications or of its fault severity cannot be achieved.

Figure 3 shows the thyristor-level electrical schematic, where TU in the figure denotes a thyristor module. The impedance test is mainly carried out by applying a voltage signal at point 1 and point 2 in the figure, and then analyzing the voltage and current responses of each thyristor level.

The equivalent circuit of a thyristor level is shown in Figure 4. For the DC impedance test, a DC voltage is applied across the valve unit. Since capacitors pass AC but block DC, the capacitors isolate the DC current and the RC damping branch can be regarded as an open circuit. Based on the measured voltage and current of the thyristor level, the impedance of the voltage-sharing branch, i.e., Rdc1 and Rdc2, can be calculated. Z ω denotes the series combination of the lead resistance R ω and the lead inductance L ω where R ω and L ω represent the series resistance and inductance of the test cable.

The parameter extraction for the damping and power-tapping circuit components is relatively complicated. By applying sinusoidal excitation voltages at different frequencies across the thyristor level, multiple sets of active- and reactive-power equations can be obtained. Solving these equations yields the conditions of the damping and power-tapping circuit components, thereby enabling fault analysis of the damping and power-tapping circuits in the converter valve.

In practical engineering, the injection device and the tested thyristor level are typically connected using copper conductors of about 3 m in length and 6 mm² in cross-sectional area, whose series resistance and inductance are on the order of several milliohms and several microhenries, respectively. Compared with the order of magnitude of the comprehensive impedance of a thyristor level (tens to thousands of ohms), the relative error introduced by the lead impedance is much smaller than the manufacturing tolerance of components (about ±5%∼±10%). To highlight the dominant resistive characteristics of the internal RC network parameters and to simplify theoretical derivations, the lead impedance is not explicitly included in the established equivalent impedance model in this paper; its impact will be evaluated and discussed in Chapter 4.

In Figure 4, we apply a sinusoidal voltage excitation with amplitude U at different angular frequencies ω . The impedances of the two series branches are Z C 2 R 2 = 1 j ω C 2 + R 2 (2) Z C 3 R 3 = 1 j ω C 3 + R 3 (3)

The complex impedance of these two branches connected in parallel is Z parallel = 1 Z C 2 R 2 + 1 Z C 3 R 3 − 1 (4)

After connecting Z parallel in series with C₁, the complex impedance becomes Z main = 1 j ω C 1 + Z parallel (5)

The final total equivalent impedance is Z eq = 1 Z main + 1 R dc 1 + R dc 2 − 1 (6)

Based on the total impedance, the total active power and reactive power can be derived as P = A 1 A 3 + A 2 A 4 B 1 2 + B 2 2 + G 1 U 2 (7) Q = A 2 A 3 − A 1 A 4 B 1 2 + B 2 2 U 2 (8)

Where A 1 = ω C 1 C 2 + ω C 1 C 3 (9) A 2 = ω 2 C 1 C 2 C 3 R 2 + R 3 (10) B 1 = ω R 3 C 1 C 3 + ω R 2 C 2 C 3 + ω R 2 C 1 C 2 + ω R 3 C 2 C 3 (11) B 2 = ω 2 R 2 R 3 C 1 C 2 C 3 − C 1 − C 2 − C 3 (12)

To prevent unintended thyristor turn-on during AC signal injection, the test platform implements comprehensive protection measures in three aspects: injection hardware design, source-impedance limitation, and safety interlocks. The impedance-testing unit uses a CPU-based controller to drive a DDS (direct digital synthesizer) and a power operational amplifier to generate the test voltage, which is applied to the anode–cathode terminals of the thyristor level under test via a high-voltage insulated flexible cable. A current sensor and a current-limiting resistor are connected in series in the output branch to form a defined source impedance; even if a short circuit occurs within the thyristor level, the injection current is constrained within a safe range. A voltage divider is connected in parallel at the output for voltage sampling, while hardware overvoltage/overcurrent comparators monitor the voltage and current in real time. Once the measured values exceed preset thresholds, the CPU immediately disconnects the analog switch and output relay to terminate the AC injection.

All AC impedance tests are performed under the conditions that the DC system is de-energized, the valve control system is set to test mode, and firing pulses are blocked. In accordance with the manufacturer’s maintenance procedures, the gate–cathode circuits of each thyristor are shorted or clamped, so that the anode–cathode injected AC voltage does not form an effective trigger voltage in the gate circuit. This prevents inadvertent turn-on from the circuit-topology perspective. Control signals between the test platform and the TCU or TTM are transmitted via optical fibers, and the power output loop is fully galvanically isolated from the optoelectronic interfaces. On the low-voltage side of the TCU, surge-absorption and overvoltage-clamping devices are deployed to suppress transient disturbances introduced into the power-tapping circuit by AC injection. The injection voltage is applied symmetrically across the anode and cathode, so the fiber interfaces experience only minor common-mode disturbances.

At the system level, the platform provides multi-stage safety interlocking. The power input is equipped with overcurrent protection as well as overvoltage and undervoltage protection, and the grounding status of both the equipment enclosure and the power supply is monitored in real time. An emergency-stop button is installed on the front panel, and a foot switch is provided on the rear panel. The CPU enables the output test voltage only when reliable grounding is confirmed, the emergency stop is released, and the foot switch is pressed. During testing, the control unit continuously monitors the grounding-detection signal, the voltage and current signals, the foot-switch status, and the emergency-stop status. If any abnormal condition is detected, including loss of grounding, output overcurrent or overvoltage, foot-switch release, or emergency-stop activation, the platform immediately cuts off the output and performs rapid discharge. An alarm pop-up is displayed on the touchscreen, and further testing is prohibited.

With the combined constraints of source impedance, injection-loop topology, and two-layer interlocking implemented in both hardware and software, unintended thyristor turn-on caused by AC injection can be avoided without compromising the blocking capability of the converter valve. At the same time, the insulation integrity and service life of the TCU and the fiber interfaces can be effectively protected.

Conventional impedance testing generally follows two approaches. In the first approach, without disconnecting the internal wiring of the converter valve, the comprehensive impedance is measured using voltage excitations at multiple frequencies, which enables qualitative fault assessment of the valve. However, this approach can only determine whether short-circuit or open-circuit conditions exist inside the valve, and it cannot detect faults of individual components in each branch. In the second approach, with the system de-energized, the wiring of the components is disconnected and individual components are tested using instruments such as a multimeter. This approach is labor-intensive and involves potential safety risks. In contrast, the method proposed in this paper enables rapid detection of faults of individual components inside the converter valve without disconnecting the electrical wiring.

Under a known voltage amplitude U , given the measured active power P ^ i and reactive power Q ^ i at different frequencies, the theoretical expressions derived from the equivalent circuit model are denoted as P i R , C and Q i R , C . Here, R = R 2 , R 3 , R dc 1 , R dc 2 , C = C 1 , C 2 , C 3 represent the resistive and capacitive component parameters to be identified, respectively.

During practical testing, the measured multi-frequency active power and reactive power are inevitably affected by noise sources such as instrument accuracy, sampling quantization, and environmental interference. Let the theoretical power under an ideal noise-free condition be.

P i true θ and Q i true θ . Then, the measured power at the i -th frequency point can be written as P ^ i = P i true θ 0 + n P , i , Q ^ i = Q i true θ 0 + n Q , i (13)

Where θ 0 is the true parameter vector of the tested thyristor level, and n P , i and n Q , i are zero-mean random noises. According to the accuracy specifications of the on-site test equipment, the noise standard deviations are set as σ P , i = α P i true θ 0 , σ Q , i = α Q i true θ 0 (14)

Where α denotes the relative measurement error.

The power error vectors are defined as Δ P i = P ^ i − P i R , C (15) Δ Q i = Q ^ i − Q i R , C (16)

To mitigate the influence caused by differences in frequency points and power magnitudes, normalized error expressions are introduced as δ P i = Δ P i P ^ i , δ Q i = Δ Q i Q ^ i (17)

Weighting coefficients ω P , i and ω Q , i are further introduced to adjust the contributions of the active-power and reactive-power errors to the overall objective. Meanwhile, considering the physical plausibility of the parameter estimates and the stability of the optimization, the following regularization term is designed: Δ X norm 2 = X − X rated X rated 2 (18)

Where X = R , C is the parameter vector to be identified, and X rated is the corresponding rated parameter vector.

The final objective function is constructed as J R , C = ∑ i = 1 n ω P , i · δ P i 2 + ω Q , i · δ Q i 2 + λ Δ X norm 2 (19)

Where λ is the regularization coefficient used to balance the error term and the regularization term. Since P R , C and Q R , C are nonlinear, the minimizer cannot be obtained analytically. Therefore, a trust-region algorithm is adopted for iterative optimization.

To ensure the physical feasibility of the solution, the identified parameters are constrained by the following bounds: X ∈ 0.99 · X r a t e d , 1.01 · X r e t e d (20)

Where X r a t e d is the rated value, and ± 1 % represents the allowable tolerance, which enforces physical plausibility. This bound constraint can effectively prevent invalid divergence during iterations and further restrict the optimization process to a feasible physical region.

Meanwhile, the termination condition for parameter updates is set as Δ X < ε , ε = 10 − 5 (21)

This condition is used as the convergence criterion to ensure that the iteration stops automatically once the required accuracy is met, thereby avoiding unnecessary computation. Based on the multi-frequency measurement set, the joint identification of key resistance and capacitance parameters is formulated and solved via the constrained multi-objective optimization in Equations 13–21 (with regularization and parameter-bound constraints). The identified parameter deviations are then used as quantitative indicators for component-level fault localization.

Based on the above analysis, this paper establishes a fault tree analysis (FTA) model for the thyristor level of a converter valve by integrating the impedance-testing results.

Top Event: The top event represents the primary fault of the overall system. In this model, the top event is defined as “fault detection of converter valves based on multi-frequency impedance testing”.

Intermediate Events: According to the impedance-testing results, the intermediate event is defined as whether the parameters of internal circuit components in the converter valve exceed the allowable tolerance range ( ± 1 % ). If the parameters do not exceed the tolerance range, the converter valve is considered fault-free. If the parameters exceed the tolerance range, it indicates that faults exist in the internal components of the converter valve.

Basic Events: The basic events correspond to specific faulty components at the thyristor level of the converter valve. By performing rapid localization and detection of internal components, the components whose identified parameters exceed the tolerance range can be determined, thereby confirming the fault condition of the internal circuits.

The established FTA model is shown in Figure 5. This model systematically correlates the impedance-testing results with faulty internal components of the converter valve, enabling step-by-step troubleshooting of internal abnormalities. Combined with measured data, the FTA can effectively identify the root causes of faults and provide guidance for subsequent maintenance.

To validate the effectiveness of the proposed multi-frequency comprehensive impedance testing method for converter valves based on fault tree analysis (FTA), a corresponding simulation model is established in MATLAB. The method is then applied to the thyristor-level impedance detection test of a converter valve in a high-voltage converter station. The equivalent circuit of the thyristor level for this type of converter valve is shown in Figure 4, and the parameter settings are taken from Table 1.

The simulation model of the conventional converter-valve impedance testing method is shown in Figure 6.

Under DC conditions and AC conditions at frequencies of 50 Hz and 2000 Hz, simulations were performed using the conventional converter-valve impedance testing model. The resulting voltage and current waveforms are shown in Figures 7–9.

In Figure 7, under the DC condition, the measured voltage is 500 kV and the current is approximately 4.9 A, from which the comprehensive impedance of the converter valve is calculated to be about 102 kΩ. In Figure 8, under the 50 Hz condition, the voltage peak is 500 kV and the current peak is approximately 340 A, yielding a comprehensive impedance of about 1,470 Ω. In Figure 9, under the 2,000 Hz condition, the voltage peak is 500 kV and the current peak is approximately 11 kA, corresponding to a comprehensive impedance of about 45 Ω. To better approximate practical test conditions, the lead impedance is estimated in terms of its order of magnitude. During testing, the injection device is connected to the converter valve using a copper conductor of approximately 3 m in length and 6 mm² in cross-sectional area. The resistivity of copper is ρ = 1.7 × 10 − 8 Ω · m . Accordingly, the series resistance is estimated as R ω ≈ 8 m Ω , and the parasitic inductance is estimated as L ω ≈ 3 μ H . At 50 Hz and 2000 Hz, the corresponding additional impedance is approximately Δ Z 50 H z ≈ 0.008 + j 0.00094 Ω , Δ Z 50 H z ≈ 0.008 + j 0.00094 Ω .

Compared with the comprehensive impedances on the order of 1,470 Ω and 45 Ω, the relative magnitude error is less than 0.1%, which is far smaller than the component manufacturing tolerances and the measurement errors in field tests. Therefore, neglecting the influence of R ω and L ω in the equivalent circuit model and parameter identification method described above is reasonable. Meanwhile, the normal impedance ranges given below can be regarded as comprehensive results that already account for lead parasitics.

The standard threshold values for the thyristor-level impedance used in this study are taken from the design specifications provided by the converter-valve manufacturer. For this type of converter valve, the required normal impedance ranges of the thyristor level are 1,430–1,510 Ω at 50 Hz and 39–49 Ω at 2000 Hz.

To avoid treating the above normal ranges as purely empirical intervals, this paper performs a tolerance-stack analysis for the comprehensive impedance at 50 Hz and 2000 Hz based on the component parameters in Table 1 and the corresponding manufacturing tolerances. Let θ = R 2 , R 3 , R d c 1 , R d c 2 , C 1 , C 2 , C 3 T denote the parameter vector of the internal RC network of the thyristor level. The impedance magnitude Z f k ; θ is computed using the equivalent circuit established in Section 2.2 and Equations 2–12. The manufacturing deviations of resistors and capacitors are set to ±5% and ±10%, respectively, namely, R i = R i , n o m 1 + δ R i , C j = C j , n o m 1 + δ C j ,

where δ R i ∼ U − 0.05 , 0.05 , δ C j ∼ U − 0.10 , 0.10 are random variables following uniform distributions. The lead impedance is included in the impedance calculation by fixing the values obtained in Chapter 4, namely, R ω ≈ 8 m Ω and L ω ≈ 3 μ H .

On this basis, a Monte Carlo method is used for tolerance-stack analysis. In each trial, a parameter sample θ n is randomly generated and substituted into the equivalent circuit model to compute the impedance magnitudes at 50 Hz and 2000 Hz, denoted as Z n 50 H z and Z n 2000 H z . Repeating this procedure N = 1,000 times yields a set of impedance samples Z n f k n = 1 N at each frequency point, based on which the mean μ z f k and standard deviation σ z f k are computed as μ Z f k = 1 N ∑ n = 1 N Z n f k ; σ z f k = 1 N − 1 ∑ n = 1 N Z n f k − μ Z f k 2 ;

The acceptance band is defined as Z min f k , Z max f k = μ Z f k − 3 σ Z f k , μ Z f k + 3 σ Z f k , which corresponds to an approximately 99% confidence interval for the impedance of a healthy converter valve. The results show that the normal impedance range is approximately 1,430–1,510 Ω at 50 Hz and 39–49 Ω at 2000 Hz, which is highly consistent with the manufacturer’s specified design indices. Therefore, this paper adopts 1,430–1,510 Ω (50 Hz) and 39–49 Ω (2000 Hz) as the acceptance bands for evaluating whether the thyristor-level impedance is normal. Comparing the calculated results with the above standard values indicates that the measured overall impedance of the tested converter valve is within the normal range. It should be noted, however, that the conventional converter-valve impedance testing method can only determine whether the overall valve is faulty, and it is difficult to further detect and localize faults to individual components in each internal branch.

In the fault tree analysis and multi-frequency comprehensive impedance testing method adopted in this paper, the resistors R_dc1 and R_dc2 in the converter-valve voltage-sharing circuit are connected in series in the same branch and have identical characteristics. Therefore, during parameter identification they can be treated as a single unknown R_dc, and the number of component parameters to be solved is reduced to six. As shown in Figure 4, six excitation voltages at different frequencies are applied, namely, 50 Hz, 150 Hz, 400 Hz, 800 Hz, 1,500 Hz, and 2000 Hz, yielding six sets of active power and reactive power measurements. The corresponding values are listed in Table 2.

Based on the obtained active and reactive power values, and using the algorithm described above, the resistance and capacitance parameters in the converter-valve damping circuit, power-tapping circuit, and voltage-sharing circuit are identified in the MATLAB simulation environment. The final estimated resistance and capacitance parameters are listed in Table 3.

On the basis of the above case study under noise-free conditions, further simulations are conducted to analyze the impact of measurement noise on parameter identification accuracy. Random noise is superimposed on the multi-frequency active and reactive power data in Table 2. Assuming that the relative accuracy of the measurement instrument is 0.5%–1%, the active power and reactive power at each frequency point are modeled as P ^ i = P i true + n P , i , Q ^ i = Q i true + n Q , i , where n P , i and n Q , i are zero-mean Gaussian noises. The standard deviations are set as σ P , i = α P i true , σ Q , i = α Q i true and the noise level α is taken as 0.5% and 1%. For each noise level, 200 groups of noisy power data are randomly generated and substituted into the multi-objective optimization model in Section 3.1 for parameter identification. The relative root mean square error (RMSE) of each component parameter is then calculated. The simulation results are presented in Table 4.

Based on the identified component parameters of the converter valve, the corresponding errors are all within the specified limits. When the measurement noise level is 0.5%, the identification RMSE of all components is below 0.5%. Even when the noise increases to 1%, the identification errors of all components remain controlled at around 1%, which is significantly smaller than their manufacturing tolerances (resistors ±5% and capacitors ±10%). Therefore, the parameter estimation and fault criteria based on multi-frequency power data exhibit good robustness under typical measurement noise levels, and they meet the requirements of electrical engineering applications. These results indicate that the proposed multi-frequency comprehensive impedance testing method for converter valves can rapidly detect faults of individual internal components without disconnecting electrical wiring. In contrast, conventional fault detection based on overall converter-valve impedance is mainly used to determine open-circuit and short-circuit conditions in the internal branches, and it cannot accurately diagnose faults at the component level. The traditional approach of disconnecting internal wiring and measuring components with dedicated instruments is labor-intensive, may damage the circuit, and involves safety risks. By integrating the multi-frequency comprehensive impedance testing method with a fault tree analysis (FTA) model, the proposed approach can effectively identify faults in components of the internal damping circuit, voltage-sharing circuit, and power-tapping circuit, enabling comprehensive diagnosis of converter-valve faults and reducing the likelihood of false alarms and missed detections.

To verify the engineering feasibility of the proposed method, a dedicated device for converter-valve comprehensive impedance testing was developed. Its physical structure is shown in Figure 10. The device adopts an integrated portable enclosure design. The upper section contains the signal injection module and an isolation transformer, while the lower section houses the control and measurement board modules. The front panel provides a power switch, range and operating-mode selectors, communication and safety-ground terminals, and an observation window, facilitating rapid wiring and status inspection by maintenance personnel in the valve hall. Figure 11 presents photographs of the internal structure of the device.

An on-site application test was carried out in the valve hall of a converter station in an HVDC project, as shown in Figure 12. The entire test was completed under the premise that the converter valve remained fully wired, and no internal connections were disconnected. Only closing the grounding switch in the valve hall was required, after which the measurements at each frequency point were performed sequentially following the procedure proposed in this paper. The field test results show that the device operated stably, and the measured results are consistent with the simulation analysis presented above. The proposed approach meets the engineering accuracy requirements for converter-valve fault detection and condition assessment, and it provides a basis for further deployment in more converter stations.