Renewable energy sources are becoming more popular. Environmental consciousness and global energy use are increasing. In contrast, natural resources such as gas, coal, and oil are finite and rapidly depleting (Das et al., 2024). Given the limited availability of these resources, it is now necessary to explore alternative energy sources (Rahimi et al., 2023). Surprisingly, the extensive use of solar energy is leading to growing concerns about the quality, dependability, and coordination of the power grid (Tayyab et al., 2023). To ensure the safe and reliable use of photovoltaic (PV) energy, various countries have established different grid codes (Nyamathulla and Chittathuru, 2023). MLIs are increasingly using PV systems as their primary energy source (Ali Khan et al., 2020). Multilevel inverters (MLIs) have become more common due to their many advantages, such as high power operating capacity, reduced switching losses, outstanding power quality, and low harmonics (Tayyab et al., 2022). These MLIs use several DC sources and power semiconductor switches to produce stepping voltage waveform. Raising their level could improve this voltage waveform (Chappa et al., 2021). It is difficult to achieve MLI reliability and efficiency because of the increased cost and component count of circuits. Three of the most common MLI structures are a neutral point clamped (NPC), a flying capacitor (FC), and a cascaded H-bridge (CHB) (Alhassane Soumana et al., 2022).

According to Omer Prabhu et al. (2020a), CHB MLI provides two different single-phase H-bridge topologies—symmetrical and asymmetrical—that are dependent on DC voltage. In contrast to symmetrical MLIs, asymmetrical ones use DC voltage sources of varying magnitudes. A standard CHB-type inverter will often have a positive, zero, or negative output (Prasad and Dhanamjayulu, 2022). Rao et al. (2018) suggested assessing the output of CHB-type inverters by aggregating the output voltages of each unit. Recently developed control methods suggest CHB inverter topologies, but the full-bridge converter changes DC step outputs into AC. The limited use of full-bridge converters stems from their inability to block higher voltages, while innovative topologies can reduce both single- and three-phase system components (Majeed Shaikh et al., 2023). Some topologies used modular MLIs to provide multilevel outputs with fewer switching devices and DC sources. These topologies use antiparallel bidirectional switches to transfer current in either direction, with minimal switching components (Kumar et al., 2022). Since cascaded subunits reduce switching-device blocking voltage, they resemble modules. The problem with such topologies is that the output level increases the number of switching devices (Sinha et al., 2018). Novel MLI designs are required to provide reduced blocking voltage, more output levels, and fewer components (Bana et al., 2019). This can reduce inverter size and price. Recent work has included a stacked H-bridge MLI architecture with basic units on each side of the complete bridge (Shaik and Dhanamjayulu, 2021).

According to Das et al. (2020), researchers have been studying cascaded MLI topology configurations. There is a singular symmetric MLI that requires fewer switches. An evolutionary algorithm creates a new design and a proven way of controlling both resistive and motor loads, keeping the output voltage stable even when loads change. Babaei et al. (2014) introduced a transistor-clamped H-bridge MLI design by enabling the various output levels for higher voltage and power ratings without necessitating an increase in component ratings. Carrier-based PWM efficiently controls the MLI, which has fewer switching losses at high switching frequencies (Siddique et al., 2020). High-frequency switching applications incur power losses. However, the topologies discussed in Omer et al. (2020b), Das et al. (2018), Sabyasachi et al. (2020), and Sarwer et al. (2020) address the challenges of more components, bulky circuits, high control complexity, THD, and low efficiency. The next step is to categorize standalone inverters as either symmetrical or asymmetrical (Prasad et al., 2021). Using the same value for each DC source indicates a symmetrical arrangement, while using different values for the DC sources results in an asymmetrical design. Meraj et al. (2020) presents two configurations ideal for low- and medium-rated solar power generation. According to Samadaei et al. (2016), FC and NPC MLIs struggle with voltage balance.

MLIs are increasingly used with PV systems as their primary energy source, and a segregated MLI architecture is best for PV integration (Alishah et al., 2017). These systems are highly efficient at electricity generation and have the added benefit of being environmentally friendly (Samadaei et al., 2018). The production of solar PV can be influenced by variations in temperature and solar radiation over time (Narendra Babu, 2024). A PV system’s efficient operation heavily relies on implementing MPPT techniques. Numerous advanced MPPT techniques have been developed to improve the performance of PV systems (Alishah et al., 2016). DC–DC converters effectively handle duty cycle fluctuation to optimize power in MPPT systems. MPPT methods such as hill climbing (HC) and perturbing and observing (P&O) are commonly used due to their straightforwardness (Shaik et al., 2023). Choosing the best MPPT methodology for an application can be challenging because each approach has its advantages and disadvantages. The HC and P&O algorithms are unable to achieve global maximum partial probability (GMPP) in partial shadow (Akbari et al., 2022).

Two-level voltage source inverters are not ideal for greater power applications due to their inability to handle high voltages and the increased electromagnetic interference caused by higher dv/dt (Krishnachaitanya and Chitra, 2021). It is necessary to address these issues to overcome these limitations. MLIs are the best option, offering advantages such as reduced voltage step, improved power quality, less switching losses, minimal harmonics, and improved electromagnetic compatibility (Mustafa et al., 2022). Additionally, as the voltage level rises in diode-clamped MLI systems, capacitor voltage balancing becomes challenging, limiting them to three levels. The utilization of FC-MLIs necessitates an increased number of DC capacitors to accommodate increased voltage levels (Hosseinzadeh et al., 2021). Nevertheless, it is possible to adjust the switching combinations and achieve balanced DC capacitor voltage (Siddique et al., 2019). CHB MLI architecture has gained in popularity and reliability because of its modularity. Nevertheless, every bridge needs a separate DC power supply. Additionally, as the levels grow, there is a greater demand for switches (Thakre et al., 2019). Topologies have been proposed as a cost-effective solution to address power quality concerns and meet high grid-code criteria (Montazer et al., 2021). These topologies are mostly derived from conventional ones; novel optimal MLI designs are required to provide high reliability, low THD, reduced blocking voltage, more output levels, and fewer components. This can reduce inverter size and price.

Some of the most important contributions of this study are:

a. The design of a standalone solar PV system integrated with a PV boost DC–DC SIMO converter and a 21-level MLI architecture that minimizes the number of components and reduces voltage stress, total size, and cost.

This study is arranged as follows. The standalone solar PV system and DC–DC boost SIMO converter are presented in Section 1. Section 2 provides a detailed explanation of the suggested 21-level MLI topology operation. In Section 3, both simulation and hardware validation results are presented. Section 4 evaluates and compares the performance parameters of various MLI topologies with the proposed MLI. Finally, Section 5 covers conclusions and future scope.

The proposed standalone solar PV system includes a selected solar panel, the 1Soltech 1STH-215-P, which has six series and two parallel units per string. Figures 2A, B display the equivalent circuit of the solar PV cell and the characteristics of the solar PV panel. D _i is the diode, R _Pa , R _Se are the resistances of parallel and series resistances, and n _pa , n _se are the number of parallel and series connected cells, respectively.

From the ideal PV circuit, the diode current can be calculated using Equation 1: I D i = I 0 e V D i γ V T − 1 , (1) where γ is the ideality constant, saturation current is I ₀, thermal voltage V_T = k T c q depends on the charge of electron q, cell temperature is T _c , and Boltzmann’s constant is k, equal to 1.3,806,503 × 10⁻²³ J/K.

Panel Output power can be calculated by using Equation 2: P P V = V P V   x   I P V . (2)

By applying KCL to the PV cell equivalent circuit,

Therefore solar PV output current can be calculated by using Equations 3, 4: I P V = I S − I D i − I p a = I S − I 0 e V D γ V T − 1 − I p , (3) I P V = n p a I S − n p a I 0 e 1 γ V T V P V n s e + R s e I P V n p a − 1 − n p a R p a V P V n s e + R s e I P V n p a , (4)

The short circuit current (I _S ) and irradiance intensity can be calculated using Equations 5, 6: I s T = I s T R β T − T R + 1 , (5) where the temperature coefficient is β, reference temperature is T _R , and short circuit current I _S(TR) values are included in the PV data sheets.

Therefore, the irradiance intensity is I s G = I s G n G G n , (6) where G _n indicates normal irradiation value.

The saturation current (I₀) can be calculated by Equation 7: I O = I s e V D i γ V T − 1   . (7)

Figures 3A, B show the connection of a PV boost DC–DC SIMO converter to solar PV panels with EINC-MPPT and solar PV-integrated with PV boost DC–DC SIMO converter for the proposed MLI. This converter consists of switches (S_B, S_L), three DC-link capacitors (C₁, C₂, C₃), and a boost inductor (L) to bring the output voltage of the PV system up to a satisfactory level for the inverter input (Rao et al., 2018). The boost converter employs an EINC-MPPT algorithm to automatically track the MPP of the PV array. The following subsections provide a comprehensive explanation of several aspects of the suggested technique.

When switch S_B is on, the output state is isolated, and an inductor (L) and a switch (S) are used to transfer the increasing input current (I_PV). The solar PV output voltage (V_PV) powers the inductor while the switch is on (T_on).

Therefore the inductor voltage can be calculated using Equation 8: V L = L d i d t . (8)

When switch S_B is off (T_off), current from the inductor is forced to flow through the load and diode (D). This diode can load the inductor (L) from the voltage source.

Therefore the output voltage of converter is V _Bdc and can be calculated Equation 9: V B d c = V P V + L d i d t . (9)

The boost converter output voltage is controlled by the duty cycle (δ) of the control switch. By altering the switch’s on-time, the output voltage can be precisely controlled.

Therefore, the DC–DC boost converter output voltage can be calculated by Equation 10: V B d c = V P V 1 1 − δ , (10) where δ = T o n T o n + T o f f .

The inductor and capacitor ratings are calculated using Equations 11, 12: L = V P V *   δ f s * ∆ I L , (11) C = I 0 * δ f s * ∆ V B d c , (12) where ΔI_L is the input current, ΔV_Bdc is the output voltage ripple factors, and f_s is the switching frequency. To obtain a reasonable estimate of the values of the inductor and capacitor, it is recommended limiting ΔI_L to 30% and generally assuming ΔV_Bdc at 5%. The characteristics of the solar PV module DC–DC boost converter requirements are detailed in Table 1.

The MPPT controller controls the performance of the boost converter by considering inputs such as temperature, solar radiation, PV array (Voc and Isc) characteristics, and DC link voltage. When the operating point varies around the maximum power point (MPP), especially in situations with rapidly changing irradiance levels, the effectiveness of conventional incremental and conductance MPPT algorithms decreases. To address these problems, an EINC-MPPT technique is implemented; Figure 4 illustrates a flowchart of an EINC-MPPT technique.

The proposed 21-level MLI architecture consists of fewer components without any inductors, capacitors, and diodes (Figure 5). It consists of only two bidirectional switches (S_A and S_B), eight unidirectional switches (S₁, S₂, S₃, S₄, S₅, S₆, S₇, S₈), and three asymmetrical voltage sources (V₁, V₂, V₃) to achieve 21 voltage levels, with each voltage step V_dc = 40 V and the maximum output voltage 400 V. The DC voltage ratio is crucial for maximizing output voltage and reducing the inverter’s TSV. Based on the recommended MLI architecture, the required component estimations follow.

The simulation results of the solar PV panel and PV-boost SIMO converter output voltages with EINC-MPPT are displayed in Figure 9A. The solar PV panel at MPP generates 112.8 V and is boosted to 400 V using a PV boost converter on the side of a SIMO converter. The PV boost DC–DC SIMO-converter simulated input and output voltages are displayed in Figure 9B. The DC link voltage response comparison for different MPPT techniques is displayed in Figure 9C. The proposed EINC MPPT technique is very effective, with a lower settlement time of 0.085 s than other MPPT techniques.

The suggested MLI circuit is modeled and simulated using MATLAB/Simulink software. The switch pulse patterns are produced at a switching frequency of 5 kHz by comparing the multicarrier signals through a 50 Hz sinusoidal signal. The modeled topology is tested for R-load as well as RL-loads. The output voltage and current waveforms of the proposed MLI are shown in Figures 10A–C. These show the output voltage and current waveforms of the MLI with R = 200Ω load and the output voltage and current waveforms of the MLI with an RL-load (R = 200Ω, L = 200 mH), respectively. The simulated FFT analysis THD of 2.06% is displayed in Figure 10D.

The experimental testing of the proposed MLI architecture was conducted, and the component specifications are listed in Table 4. Power-switching IGBT (CM75DU-12H) devices, optocouplers (MCT2E), and asymmetrical DC sources are used to implement this hardware prototype. The dSPACE RT1104 controller is used to generate the switching sequence for each switching device, using optocouplers for activation. The hardware prototype was tested with various load conditions, achieving a 21-level output voltage of 400 V. The voltage and current output waves were examined, and the results were captured using a DSO connected to the prototype via a differential probe. A hardware prototype of the suggested MLI is shown in Figure 11A.

Figure 11B presents the experimental output voltage waveforms of the solar PV panel as well as the PV-boost converter. Figure 11C presents the input and output voltages of the PV-boost DC–DC SIMO converter.

Figures 12A–D present the output voltage as well as the voltage and current waveforms of a proposed MLI for R = 200Ω load and RL-load (R = 200Ω, L = 200 mH), as well as the output voltage waveform for various modulation index (Ma) values, respectively. Figures 13A–D present the output current behavior when the dynamic load changes from R- to RL-load. Figures 14A–E present the output current behavior when the dynamic load changes from RL- to R-. The output voltage THD is 2.26%—in line with IEEE standards.

TSV is extensively used to choose power switches. All power-switching devices in the design have an influence on TSV (Prasad and Dhanamjayulu, 2022). To calculate the blocked voltage across power-switching devices, V_Sbi = V_i and V_Suni = 2V_i are the voltage stresses on the bi- and uni-directional switches, respectively, where i = 1, 2, n and n is the power switch.

Therefore, the maximum output voltage is calculated using Equation 20: V o , ⁡ max = 10 V dc = 400 V . (20)

The maximum blocking voltage (MBV) of particular switches can be calculated using Equations 21–23: MBV SA = MBV SB = 2 V dc , (21) MBV S 1 = MBV S 2 = MBV S 3 = MBV S 4 = 3 V dc , (22) MBV S 5 = MBV S 6 = MBV S 7 = MBV S 8 = 7 V dc . (23)

The normalized voltage stress (NV_stress) is defined as the ratio of the switch’s V_stress to V_o,max. The V_stress is the true voltage stress. Respective switch voltage stress values are listed in Table 5.

Figures 15A, B show each switch voltage stress distribution and the normalized voltage stress (%). The MLI design’s maximum output voltage is 10V_dc, which has 21 levels; however, the algebraic total of DC sources exceeds the switch’s MBV (7V_dc). Despite unequal voltage stress across the switches in the suggested MLI architecture, four switches have a maximum voltage stress of 7V_dc (S₅, S₆, S₇, and S₈). The smallest voltage stress is 20% of the two power switches (S_A and S_B) and 30% intermediate voltage stress of the remaining four switches (S₁, S₂, S₃, and S₄). Therefore, to save money, the suggested MLI design aims to increase DC source intake while minimizing TSV and switches.

The TSV is given as the algebraic sum of MBV across individual switches and is expressed in Equations 24, 25, providing the TSV_PU value thus: T S V = M B V S A + M B V S B + M B V S 1 + − − − + M B V S 8 , (24) TSV PU Proposed = TSV V O , max . (25)

The suggested topology TSV^Proposed can be calculated using Equations 26, 27: TSV Proposed = 2 MBV SA + 4 MBV S 1 + MBV S 5 = 4 V dc + 4 3 V dc + 7 V dc = 4 V dc + 12 V dc + 28 V dc TSV Proposed = 44 V dc , (26) TSV PU Proposed = 44 V dc 10 V dc = 4.4 . (27)

Therefore, the suggested MLI’s peak inverse voltage (PIV) can be calculated by Equation 28: P I V P r o p o s e d = N l e v − 1 = 20 V d c . (28)

The cost function (CF) can be calculated using some quantitative aspects of the suggested topology, such as a number of DC sources (N _DC ), switches (N _Swi ), gate driver circuits (N _Dri ), diodes (N _Dio ), capacitors (N _Cap ), and the per unit value of TSV (TSV _pu ) of the topology (Prasad et al., 2021). Therefore, the CF can be calculated by Equation 29: C F = N S w i + N D C + N D r i + N D i o + N C a p + α   T S V P U . (29)

In this calculation of the cost function, the weight coefficient α value should be considered lower than 1 as well as larger than 1. In order to best evaluate the cost function, the developed MLI uses an approximation of α values of 0.5 (<1) and 1.5 (>1) (Shaik and Dhanamjayulu, 2021). Equation 30 calculates the cost function per level: C F N L e v = N S w i + N D i o + N C a p + N D r i + N D C + α   T S V P U N L e v . (30)

Therefore, CF/N _Lev for the suggested 21-level MLI topology with α values of 0.5 and 1.5 are 1.20 and 1.409, respectively.

Two notable power losses occur in multilevel inverters: conduction (P _Cond ) and switching losses (P _Swil ). Total conduction loss is determined by summing the conduction losses of both IGBTs (P _CSW ) and anti-parallel diodes (P _CD ) along the current path (Prasad and Dhanamjayulu, 2022). This can be expressed using Equations 31, 32: P C o n d t = P C S W t + P C D t , (31) P C o n d t = V S w i + R S W i i m β t + V D i o + R D i o i m t i m t , (32) where i _m (4A) is the peak output current. The threshold voltages for power switches and diodes are V _Swi (4 V) and V _Dio (0.7 V). Similarly, R _Swi (0.001Ω) and R _Dio (0.001Ω) represent the power switch on-state resistance and diode, respectively. The datasheet specifies β (0.01) as the power switch specification constant. If N _Swi and N _Dio are the switches and diodes are conducting at the same time (t) to produce each level, then the average conduction loss is expressed using Equation 33: P C o n d = 1 2 π ∫ 0 2 π N S w i t P C S W t + N D i o t P C D t d t . (33)

Switching loss (P _Swil ) is the amount of power used when the switch turns on and off. This loss is calculated for the switch and the antiparallel diode. Equations 34–36 can be used to calculate the turn-on and -off energy loss (E _on , E _off ): E o f f − q = ∫ 0 t o f f v t i t d t = ∫ 0 t o f f V S W q t o f f t − I t o f f ( t − t o f f d t , (34) E o f f − q = 1 6 V S W q I t o f f . (35)

Similarly, E o n − q = ∫ 0 t o n v t i t d t = ∫ 0 t o n V S W   q t o n t − I ′ t o n ( t − t o n d t E o n − q = 1 6 V S W q I ′ t o n . (36)

The time it takes to turn the switch off is t _off , the time to turn it on is a t _on , and the corresponding losses from the switch are E _off-q and E _on-q , respectively. Although V _{SW q} represents the voltage of the switch when it is in the off state, I and I ^I represent the currents before and after the switch is turned on, respectively. The total switching losses can be calculated by Equation 37: P S w i l = f ∑ q = 1 N S W ∑ i = 1 N o n − q E o n   q i + ∑ i = 1 N o f f − q E o f f   q i . (37)

The fundamental frequency is denoted by f, N _on-q , and N _off,-q , and the number of times that the q ^th switch is turned on or off during a single fundamental cycle. Therefore, the overall power losses is expressed using Equation 38: P T o t a l   = P C o n d + P S w i l . (38)

The output power can thus be calculated by Equation 39: P o u t p = V r m s * I r m s . (39)

The total efficiency (η) can be calculated using Equation 40: %   η = P o u t p P i n p = P o u t p P o u t p + P T o t a l   x 100 , (40) where P _outp and P _inp are the output and input powers. Table 6 summarizes the power losses and efficiency of the suggested MLI. The efficiency for various loads is graphically illustrated in Figure 16.

The reliability study determines the equipment’s predicted lifetime and failure rate, which are crucial to determining the health of any electronic device. Manufacturing organizations can profit from this reliability study as they seek long-lasting, high-performing, and low-maintenance products, and the industry can also estimate the mean time-to-repair and mean downtime to resume operations (Figure 17A). Therefore, an estimation of how long a device will survive is essential. To determine a device’s reliability, several factors are considered.

MTTF_T and FR_T are the key reliability assessment requirements. The hazard rate (λ_T) is a prediction of failure over a certain timeframe. When FR is time-invariant, R(t) is reliability. Approximation and precise methods are preferred in power electronic circuit reliability testing. The mean time to the first failure is initially calculated to determine device durability. A high mean-time-to-failure (MTTF_T) indicates reliability. This and the failure rate (FR_T) of a device can be determined using MIL-HDBK 217E standard handbooks (Shaik et al., 2023). The approximation approach simplifies and accurately predicts FR_T values for switches, diodes, and capacitors (mentioned in detail in Table 7), and the flowchart is shown in Figure 17B to calculate the MTTF_T value.

Furthermore, as shown in Figure 17C, the suggested MLI keeps its self-voltage balanced, a unique quality that makes it suitable for a wide range of applications such as solar PV systems, fuel cells, battery-powered applications, and industrial generators. In addition, the suggested MLI might be used in medium-power micro-grids and grid configurations, offering a reliable solution for the problem of remote electrification.

The total MTTFT is estimated from power electronic circuit element FR values. Equation 41 is used to calculate λ_T: λ T = λ PS × N Swi + λ PD × N Dio + λ PC × N Cap . (41)

Equation 42 is used to calculate the power electronic circuit MTTF_T: MTT F T = 1   λ T . (42)

The suggested MLI architecture was compared with numerous quantitative features of the existing MLI topologies, including the number of DC sources (N _DC ), power switches (N _Swi ), gate drivers (N _Dri ), diodes (N _Dio ), capacitors (N _Cap ), and component count per number of levels (CC/N _Lev ). When it comes to qualitative comparisons such as the TSVpu, THD, CF, FR_T, and MTTF_T features, Table 8 presents quantitative and qualitative comparisons of the proposed 21-level MLI with existing topologies. All these comparisons indicate that the suggested 21-level MLI architecture is more economical, cost-effective, and achieves better performance outcomes.