GRID-TIE inverters are widely used in various distributed generation (DG) systems powered by solar photovoltaic (PV) arrays or wind power. Among the control algorithms used in the grid-tie inverters, the hysteresis control algorithm has many advantages compared with the traditional PID (Proportion Integration Differentiation) control algorithm: it can track any form of the command signal, the tracking error accuracy can be controlled and adjusted, and the control bandwidth is extremely high (Chavali et al., 2022). Therefore, it is widely used in harmonic suppression, noise filtering, and other occasions to improve power quality and electromagnetic protection in micro-grid (Viswadev et al., 2020; Wang et al., 2014). Hysteresis control algorithms have undergone development from analog hysteresis control to digital hysteresis control. Analog hysteresis control has high tracking accuracy and good control effect because the controlled signal is a real-time continuously changing analog quantity, but it relies heavily on the performance and cost of analog chips, which leads to its application being limited (He et al., 2013). In contrast, digital hysteresis control is the future direction because of its flexibility and low dependence on the microchip, which has great demand in many applications (Acuna et al., 2015; Davoodnezhad et al., 2014a). However, the accuracy of digital hysteresis control is limited by the discretization and sampling rate (Wang and Wang, 2013), which has a great influence.

As shown in Figure 1, the blue and orange waveforms in the first graph of figure (a) and (b) represent the bandwidth of the hysteresis control, indicating the upper and lower limits of the error tolerance. The red waveform indicates the command signal and the green waveform indicates the actual controlled signal. The red waveform in the second graph of figure (a) and figure (b) indicates the error signal. The blue signal indicates the absolute value of the bandwidth. From the comparison of the graphs, it can be seen that under a high sampling rate, the error current is close to a continuous analog signal, and the error is always kept within the hysteresis bandwidth during all the control process. While under a low sampling rate, it is difficult to accurately capture the signal at the moment of intersection of the error signal and the bandwidth, making the error signal greatly exceed the allowed boundary range, showing low precision and poor control effect.

In actual products, the ADC sampling rate of the digital controller cannot be too high, otherwise the control algorithm cannot be completed during one control period before the next data refresh. Therefore, it is of great practical importance to study how to reduce the impact of sampling rate on digital hysteresis control under the premise of ensuring control accuracy.

In the past few years, several improvements have been proposed, particularly focusing on reducing the hysteresis control equivalent sampling frequency and improving the current tracking effect (Malesani et al., 1997; Carl et al., 2009). In (Malesani et al., 1997; Stefanutti and Mattavelli, 2006; Hu et al., 2014), several digital hysteresis control methods based on oversampling and virtual sampling were proposed, but the sampling rates are high, the amount of data is too large, and the authenticity of the virtual sampling data needs to be further verified. In (Chen and Kang, 2011), a hysteresis control method with online prediction of sampling time is used, which can predict the next sampling time to ensure the effect of current tracking at a reduced sampling rate, but this method does not take into account the problem of inductor parameters changing with current, making the predicted values deviate in the practical application. In Carl et al. (2009), the error of the hysteresis control at different stages is analyzed and a method to increase the current tracking accuracy by changing the number of switch levels at the moment of maximum error is proposed, but the switching process of this method is complicated and the loss to the device is great.

In this paper, a novel online sampling prediction control method without inductance is proposed. With the proposed scheme, the following advantages are obtained. (1) the digital hysteresis equivalent sampling frequency is reduced compared with the oversampling digital hysteresis method by the prediction control method. (2) the control accuracy is guaranteed by analyzed the error current within and beyond the hysteresis bandwidth so that the hysteresis error is fixed. (3) the problem of inductor parameters changing with current to the hysteresis control is solved.

The rest of this paper is organized as follows. In Section 2, the sampling prediction method of the digital hysteresis control for the three-level inverter is derived and the effect of inductor parameters on the control accuracy is analyzed. In Section 3, the inductance-free sampling time online prediction control method is derived. In Sections 4 and 5, the simulation and experimental results are presented in detail.

According to the traditional hysteresis control algorithm (Chen et al., 2012; Jiao et al., 2014) (take the current-source power electronic converter as an example), if the current sampling value is located on the boundary of the hysteresis bandwidth at each sampling moment, the converter will act at this time, and the sampling moment is valid; On the contrary, if the current sampling value at the sampling moment is within the bandwidth of the hysteresis control, the converter does not act, so the sampling point does not affect the control system, then it is meaningless. Therefore, the minimum sampling rate occurs at the moment when all the sampling points of the controlled current are located at the intersection of the bandwidth boundary of the hysteresis control (Liu and Maswood, 2006; Mohseni and Islam, 2010; Wang and Li, 2013), as shown in Figure 2.

As shown in Figure 2A, the red sampling points are inside the upper and lower boundary of the hysteresis bandwidth, which cannot trigger the converter to switch, and the sampling value is meaningless to the hysteresis control system; on the contrary, in Figure 2B, as each sampling current value is located on the upper and lower boundary of the bandwidth, it just makes the converter to switch, which is timely and effective. Due to the changes in the control reference, hysteresis bandwidth, and hardware parameters as well as external disturbances in the actual control system, the interval between sampling points or the sampling rate, is bound to change constantly if all sampling points are located on the bandwidth boundary of the hysteresis control, as shown in Figure 2B. Therefore, simply using the traditional ideal fixed sampling rate as shown in Figure 2A cannot meet the requirements of the actual sampling interval changes, which poses a challenge to reduce the sampling rate while ensuring the control accuracy. Therefore, it is important to study how to improve the effectiveness of digital hysteresis control and how to reduce the equivalent sampling rate.

According to the analysis, it can be known that: at each sampling point, the time required for the current to reach the next bandwidth intersection position can be deduced from the actual sampled current value, as well as the commanded current given by the algorithm, the upper and lower limits of the hysteresis bandwidth, and this time will be set as the next sampling period, then the ideal equivalent minimum sampling rate can be obtained in Eq. 1, as shown in Figure 3. Δ T = t n + 1 − t n = B u p n − i L r n k i L r n . (1)

Where B u p n = i r e f n + H , and H is the hysteresis bandwidth. k i L r n indicates the slope of current at sampling time t n .

As can be seen from the above equation, the slope of the current has a critical impact on the sampling rate.

The following is an example of a Type I and Type T three-level inverter.

From the single-phase topology of the three-level inverter, the series equivalent resistance R r of the inverter-side inductor L r is neglected, and the general LCL-type filter is usually designed with a grid-side inductor L g ≪ L r , so the voltage drop on the grid-side inductor L g can also be neglected, which leads to: L r d i L r t d t = V x t − E t (2)

In Eq. 2, the L r represents the inverter-side inductor in Figure 4, the V x t represents the terminal voltage of the inverter, typically the PWM (pulse width modulation) voltage, and the E t represents the grid voltage.

Then, according to the modulation law of the three-level switching state (Shen et al., 2011; Stefanutti and Mattavelli, 2006), the following Table 1 of switching states can be obtained.

In Table 1, S x ( x = 1 a , 2 a ) represent the state of the switch in one arm at the bridge of the three-level inverter. E g represent the grid voltage. And the first row of Table 1 in orange color represents the positive level of the three level inverter, the last row in blue color represents the negative level, and the middle two rows in gray color represents the zero level of the three level inverter.

From this, it can be seen that: k i L r = d i L r d t = S 1 a × U d c 2 − E g L , E g > 0 S 2 a − 1 × U d c 2 − E g L , E g < 0 (3)

In Eq. 3, k i L r = d i L r d t indicates the slope of the current of the inverter-side inductor. The S 1 a and S 2 a represents the switching state of the first two of four switching devices in one arm of the inverter in Figure 4. And the U d c represents the total voltage of the DC capacity in inverter.

Thus, the conventional sampling time prediction algorithm for digital hysteresis control of three-level converter can be obtained as follows: Δ T = t n + 1 − t n = B u p n − i L r n k i L r n k i L r n = S 0 × U d c 2 − E g L S 0 = S 1 a   , E g t > 0 S 2 a − 1 , E g t < 0 (4) where S 0 is the switch state corresponding to the moment of the sampling point. The Δ T is the period of the digital hysteresis control.

Combined with the above analysis, it can be seen that the sampling moment predicted by the traditional digital hysteresis control algorithm is closely related to the inductance L . However, in actual products, due to cost and process limitations, the total amount of flux that the core of the inductor can hold is certain, and when the flux is saturated, it makes the inductance change drastically. Therefore, the corresponding inductance is different for various current output conditions. Usually, manufacturers design the nominal inductance according to the empty load current, which can cause the actual inductance to drop sharply to less than one-third of the nominal inductance when working at full load current. This brings inaccuracy to the digital hysteresis sampling time prediction. As shown in Figures 5, 6.

From the previous analysis, it can be seen that how to accurately predict the sampling time when the actual inductor changes due to various current becomes a key step in reducing the equivalent sampling rate and improving the effectiveness of digital hysteresis control. Moreover, from the previous analysis, it is known that the predicted sampling rate varies due to a series of factors such as external disturbances in the sampling of controlled current, which inevitably cause changes in the control frequency (Ramchand et al., 2012; Shukla et al., 2011). Thus, it creates a big problem in the thermal loss of the converter, and the design of the LCL filter, especially the design of the inductance. Therefore, how to work with a relatively fixed switching frequency when both sampling time and inductance of the filer inductor change becomes a top priority. According to the literature (Davoodnezhad et al., 2014b), the bandwidth of the digital hysteresis control can be designed to change to ensure a fixed switching frequency when the sampling rate varies (Song et al., 2014; Zeng et al., 2004). Then, the bandwidth of the quasi-fixed frequency digital hysteresis control based on three-level converter with LCL filter can be expressed in Eq. 5 as follows: H = U d c 2 L × f s m 1 − 2 m , m = E g t U d c (5)

Where U d c indicates the total DC voltage value on the DC side of the three-level converter, f s indicates the desired fixed target switching frequency, L indicates the total AC side filter inductance, and m = E g t U d c indicates the control modulation index at time t .

From the equation, it can be seen that the variation of the bandwidth in the hysteresis control can be inferred from the target expectation fixed switching frequency f s . Moreover, the bandwidth H is changed at a frequency of 2 times the grid frequency (the square function of the control modulation index, which is the same as the AC grid voltage E g t ). Since the switching frequency of the hysteresis control is typically in tens k H z , which is much larger than 2 times the grid frequency, the bandwidth can be approximated as constant within each switching cycle. Moreover, for the inverter, the frequency of the command signal it tracks is also the same as grid, which can also be considered approximately constant during each switching cycle.

So, assume: H k − 1 ≈ H k , i r e f k − 1 ≈ i r e f k , the upper and lower limits of the bandwidth: B u p = i r e f + H and B d o w n = i r e f − H can also be expressed as: B u p k − 1 ≈ B u p k B d o w n k − 1 ≈ B d o w n k (6)

Thus, when the sampling point is at the intersection of the current and the bandwidth, there is Δ T p r e = B d o w n k − B u p k − 1 k i L r = B u p k − B d o w n k − 1 k i L r = 2 H k i L r (7)

By substituting Eqs (6), (7) into the previous Eq. 4, we can get:

After simplification, Eq. 8 can be expressed as: Δ T p r e = 2 T s m 1 − 2 m S 0 − 2 m (9)

Where S 0 = S 1 a , E g t > 0 S 2 a − 1 , E g t < 0 .

As can be seen from Eq. 9, the predicted sampling time is only related to the desired switching period and the control modulation index function m , independent of parameters such as the inductor L . Therefore, the problem of the nonlinearity between the inductance and the output current is solved for the prediction time at steady state.

The previous equation is derived to be effective when the sampling point is just at the intersection of the current and the bandwidth, and after analysis, it is also effective when the current at the sampling moment exceeds the upper or the lower limits of the bandwidth, which can be corrected to: Δ T p r e = 2 T s m 1 − 2 m S 0 − 2 m , Δ i k ≥ H (10) where Δ i k indicates the error current.

However, the sampling point is likely to deviate from the bandwidth because of the delay in the sampling process, the inertia of the system, and the actual presence of delay in the PWM control. Thus, at some moments when the current value is less than the hysteresis bandwidth, a correction to the prediction Eq. 10 is required:

From Figure 7, it can be seen that:

when Δ i k < H , since Δ i k = i r e f k − i k , we can get: e k = H − Δ i k .

then, the correction of sampling period is t c = e k k i L r k − 1 .

Due to k i L r k − 1 = i k − i k − 1 Δ T p r e k − 1 , according to the above equations: t c = H − Δ i k i k − i k − 1 × Δ T p r e k − 1 (11)

Therefore, t c is the correction formula when the error current is less than the band.

According to Eq. 10 and Eq. 11, the online prediction algorithm based on inductance-free sampling time can be expressed as Δ T p r e k = 2 T s m 1 − 2 m S 0 − 2 m , Δ i k ≥ H H − Δ i k i k − i k − 1 × Δ T p r e k − 1 , Δ i k < H (12)

Where: Δ i k = i r e f k − i k S 0 = S 1 a , E g t > 0 S 2 a − 1 , E g t < 0 ,

S x ( x = 1 a , 2 a ) indicates the current switch status at the sampling moment, as described in Table 1.

In order to verify the above proposed control method, a simulation comparison analysis was conducted with a LCL type filter based on three-level neural-point-clamped inverter as an example, and the simulation parameters are listed in Table 2.

In order to further verify the theoretical feasibility of the proposed method and the accuracy of the simulation analysis, an experimental verification was conducted. The selected experimental equipment is a 100 kW type I three-level APF. The experimental parameters are shown in Table 3.

The instrumentations used in the experimental setup in Figure 13 are list as follows: the grid-tie inverter is a 100 kW Type I three-level NPC inverter. The inductors are custom-made magnetic core inductors with 1.5 mH at empty load. The controller is used with a DSP 28335 control board with maximum 16 ADC channels and 12 PWM channels. The Oscilloscope is a ZLG 3024PLUS 4 channel scope with 300 MHz bandwidth. And the grid is connected through an isolated transformer with 500 kV A.

In this paper, a digital hysteresis control method for three-level inverter based on online prediction of sampling time without inductance is proposed. Through the sample time prediction and correction, the dependence on high sampling rate in traditional hysteresis control is reduced, while the accuracy is improved by keeping the error within the hysteresis band all the time. Furthermore, the impact of inductor parameter changing with different current is eliminated by cancelling the use of inductance during the control process. The effectiveness and robustness of the proposed control method are not only carried out by theoretical analysis and mathematical derivation, but also validated by simulation and experiment.