This paper begins by providing a brief introduction to the topology of the single-phase three-leg UPQC. As shown in Figure 1, the parallel compensation port consists of leg a, leg b, and parallel interface filters (L _p1, L _p2, and C _p), while the series compensation port consists of leg b, leg c, and series interface filters (L _s and C _s). When the grid voltage V _g is not equal to the rated voltage V _N, the series compensation voltage V _sc will be provided through the series compensation port. As a result, the load voltage V _L can reach its rated value. Additionally, the series compensation port can compensate for the harmonic components of the grid voltage. The device also compensates for the harmonic currents generated by non-linear loads by providing the parallel compensation current I _pc through the parallel compensation terminal. Then, the grid current I _g can be sinusoidal. In addition, the reactive power component of the load current can be compensated through this single-phase three-leg UPQC. The two converters share a DC bus capacitor C _dc, and the DC bus voltage V _dc is controlled using a parallel compensator.

There are three control objectives for the parallel compensation terminal, including stabilizing the DC bus voltage, compensating for the load reactive current, and compensating for the load harmonic current. Therefore, the control strategy needs to be individually formulated around these three control objectives.

For the control of the DC bus voltage, first, the differential equation of the DC bus capacitor is derived as follows: I dc = C dc d V dc d t , (1) where I _dc represents the current flowing into the DC bus. Therefore, the expression of the DC bus voltage can be obtained from Eq. (1) V dc = 1 s C dc I dc . (2)

According to Kirchhoff’s current law, it can be known that I _dc = I _pc. However, the reactive component of I _pc only causes a ripple voltage at twice the frequency on the DC bus, while its active component I_pc,d plays a role in stabilizing the DC bus voltage. By designing a controller based on Eq. (2), the stability of the DC bus capacitor voltage can be achieved by controlling the active component I _pc,d of the parallel compensating current. The control strategy for I _pc,d is as follows: I pc , d = k p , dc + k i , dc s V dc ref − V dc , where k _p,dc represents the proportional coefficient of the PI controller and k _i,dc represents the integral coefficient of the PI controller. The overall control block diagram of the entire control system is shown in Figure 2.

The load current can be decomposed into three parts as follows: I L = I L , d + I L , q + I L , h , (3) where I _L,d represents the active component of the load current, I _L,q represents the reactive component of the load current, and I _L,h represents the harmonic component of the load current. To achieve compensation for I _L,q and I _L,h, it is necessary to first extract I _L,q and I _L,h and then control the parallel output port to output currents in the opposite direction of I _L,q and I _L,h, which can be implemented by the current closed-loop controller. According to Kirchhoff’s current law and Eq. (3), the grid current will no longer contain any reactive or harmonic components. Based on this idea, the control strategy proposed in this paper is given as follows: first, we obtain the reference value of the effective active current that is required to maintain the stability of the DC bus voltage based on the control loop of the DC bus voltage; then, it is multiplied by 1/K of the collected real-time grid voltage to generate the active current output reference using the parallel compensator, denoted as I _d ^ref, where K generally takes the rated grid voltage amplitude. Therefore, the reference current of the parallel compensator’s output, denoted as I _pc ^ref, is given as I pc ref = I d ref − I L . (4)

Since the active current reference for the DC bus voltage loop has been given, the active current reference for the parallel port output I _pc ^ref, obtained from Eq. (4), represents the opposite current of the load reactive current I _L,q and the load harmonic current I _L,h. Then, the output current I _pc of the parallel port is controlled in real time using a current closed-loop controller. The current controller adopts a proportional resonant (PR) controller, which is denoted as G _cur,p. Therefore, the expression for the drive signal of the parallel inverter is given as d p = k p , cur , p + ∑ h 2 k r , h , cur , p ω cut s s 2 + 2 ω cut s + h ω 0 2 I pc ref − I out , p , (5) where k _p,cur,p represents the proportional coefficient of the PR controller, k _r,h,cur,p represents the resonance coefficient for each frequency h, ω _cut is the resonant bandwidth control parameter, and ω ₀ is the natural angular frequency. The detailed control strategy for the parallel compensator is shown in Figure 3. It can be seen from the figure that the grid-connected control uses the instantaneous value of V _g instead of the real-time phase angle of V _g.

The circuit structure of the parallel port and the overall control block diagram are shown in Figure 1, where L _p1, L _p2, and C _p constitute the interface filters of the parallel inverter. Therefore, the expression for the output current I _out,p of the parallel inverter with respect to the inverter drive signal d _p is given by the following: I out , p = d p G i , dc , (6) where G _i,dc represents the transfer function of the inverter drive signal d _p to I _out,p, and its expression is given as follows: G i , dc = V dc 1 + s 2 L p 2 C p s L p 1 + L p 2 + s 3 L p 1 L p 2 C p . (7)

Based on the control block diagram and the topology of the single-phase three-leg UPQC, the closed-loop transfer function Φ _p of the parallel port output current I _pc, with respect to the output current reference I _pc ^ref, can be obtained as follows: Φ p = G cur , p K PWM G i , dc 1 + G cur , p K PWM G i , dc , (8) where K _PWM is the gain of PWM modulation, which represents the proportional coefficient between the controller output variable and the converter output voltage. From Eqs (6–8), the Bode plot of this closed-loop transfer function is obtained, as shown in Figure 4 and the parameters for plotting the Bode plot can be found in Table 1. From this graph, it can be observed that at odd harmonics frequencies, the magnitude response is 0 dB and the phase response is 0°. This indicates that the amplitude of the parallel port output current I _pc is equal to the amplitude of the output current reference I _pc ^ref, and the phase of the parallel port output current I _pc is equal to the phase of the output current reference I _pc ^ref, i.e., I _pc = I _pc ^ref. Then, the control requirements can be satisfied.

The series compensation port has two control objectives. First, when the grid voltage exceeds the limits, it provides compensating voltage on the line to maintain the load voltage at the rated value. Second, it aims to reduce the harmonic components in the compensated grid voltage and increase the sinusoidal quality of the load voltage. To achieve these objectives, similar to the parallel compensation strategy, a PR controller is selected as the control function for the voltage loop and the current loop. The specific control block diagram is shown in Figure 5. The d-axis voltage V _d and the q-axis voltage V _q can be obtained through a second-order generalized integrator (SOGI), where the transfer functions of V _d and V _q relative to V _g are, respectively, as follows: D s = V d V g = k SOGI ω 0 s s 2 + k SOGI ω 0 s + ω 0 2 , (9) Q s = V q V g = k SOGI ω 0 2 s 2 + k SOGI ω 0 s + ω 0 2 , (10) where k _SOGI is the filter gain coefficient. It is evident from Eqs (9, 10) that when the frequency of V _g is ω ₀, the amplitude gains of D(s) and Q(s) are both 1 and the phase angle gains are 0 and −90°, respectively. As a result, the grid voltage amplitude V _g ^amp is as follows: V g amp = V d 2 + V q 2 . (11)

We compare V _g ^amp from Eq. (11) with the rated grid voltage amplitude and perform some simple calculations, as shown in Figure 7, to obtain the load voltage reference, which has an effective value of V _N and the same phase as the grid voltage.

The circuit structure of the series port and the control block diagram of the overall system are shown in Figure 1, where L _s and C _s constitute the interface filter of the series inverter. The expression for the compensation voltage V _sc in terms of the inverter drive signal d _s is given by the following: V sc = d s G v , dc , (12) where G _v,dc represents the gain of the inverter drive signal d _s with respect to the output voltage V _sc, and its expression is shown as follows: G v , dc = V dc 1 + s 2 L s 1 C f . (13)

Similar to the parallel port, d _s is determined by the control system. Based on the control block diagram, as shown in Figure 5, the expression for d _s can be obtained by the following: d s = G vol , s G cur , s K PWM 1 + G cur , s G PWM G v , i V sc ref − V sc , (14) where G _vol,s represents the transfer function of the voltage controller and G _cur,s represents the transfer function of the current controller, both of which are PR controllers. Moreover, k _p,vol,s and k _r,h,vol,s are the proportional coefficient and the resonance coefficient of the voltage controller for the series compensator, respectively; k _p,cur,s and k _r,h,cur,s are the proportional coefficient and the resonance coefficient of the current controller for the series compensator, respectively. G _v,i represents the transfer function of the load current to the output voltage of the series inverter, and its expression is shown as follows: G v , i = s V dc C f 1 + s 2 L s 1 C f . (15)

Therefore, the closed-loop transfer function Φ _s of the series port output voltage V _sc with respect to the output voltage reference V _sc ^ref can be obtained as follows: Φ s = G vol , s G cur , s K PWM G v , dc 1 + G cur , s K PWM G v , i + G vol , s K PWM G cur , s G v , dc . (16)

From Eq. (12–16), the Bode plot of the closed-loop transfer function Φ _s is obtained, as shown in Figure 6. The parameters for plotting the Bode plot can be found in Table 1. From the graph, it can be observed that at odd harmonic frequencies, the magnitude response is 0 dB and the phase response is 0°. This indicates that the amplitude of the series port output voltage V _sc is equal to the amplitude of the output voltage reference V _sc ^ref, and the phase of the series port output voltage V _sc is equal to the phase of the output voltage reference V _sc ^ref, i.e., V _sc = V _sc ^ref. Then, the control requirements can be satisfied.