A more-electronics power system consists primarily of generators and loads that interface with the power grid through individual power converters (Fang, 2021a; Fang et al., 2017; Fang et al., 2019). These power converters feature many different topologies, among which single-phase and three-phase bridges are popular, such as the H-bridge converter shown in Figure 2 (Das, 2019a; Fang et al., 2021b). This article is applicable to various grid-forming converters. As one example, we will focus primarily on single-phase H-bridge grid-forming converters.

The H-bridge converter is power electronic equipment that consists of a DC voltage source V_dc, four semiconductor switches, and passive filters. As the proposed lattice power grids allow the removal of passive filters, we illustrate the operation of H-bridge converters via Figure 2 (Das, 2019b). As seen, an H-bridge converter can take on one of the four states:

1) The H-bridge outputs a positive voltage.

Existing grid architectures for more-electronics power systems do not allow high-voltage applications of grid-forming converters, only allowing for current sharing through parallel operation (Lin, 2020). To allow for high-voltage DC and AC applications, we can turn to the benefits of multilevel converters.

In recent decades, multilevel converters have emerged as a technology of substantial interests due to their wide-ranging applications. Common multilevel converters include CBC and MMC (Das, 2019a; Fang et al., 2021a; Fang et al., 2021b). Such power converters often consist of half-bridge or H-bridge submodules in serial connection to allow for the creation and transmission of high voltages using lower-voltage components. As a result, multilevel converters have found a wide variety of applications across the field of power electronics (Fang et al., 2021b; Flourentzou et al., 2009). The concept of multilevel converters can be expanded to more-electronics power systems as well, with each grid-tied power source (solar PV, wind turbine, etc.) representing a submodule in a power grid (Fang et al., 2017; Fang et al., 2019; Fang, 2021a).

A drawback of existing multilevel converters is that serial connection does not allow for current sharing, thus limiting current ratings. Recent research has investigated the potential of multilevel converters that allow for parallel connectivity (Goetz et al., 2015; Goetz et al., 2017; Das, 2019a; Fang et al., 2021a; Fang et al., 2021b). Connecting CBC branches in parallel allows for a greater amount of current to be delivered and the use of components with lower current ratings (Fang et al., 2021b).

The square lattice power grid consists of several grid-forming H-bridge converters connected in a lattice structure (see Figure 3A). Lattice power grids can be modeled using graph theory, with each H-bridge converter represented as an edge and each terminal between converters represented as a node (Fang, 2021b; Fang and Goetz, 2021; Mei et al., 2022). Figure 3B depicts the graph model of the lattice power grid depicted in Figure 3A.

We model the lattice power grid architecture depicted in Figure 3 as a square lattice graph, whose topology forms a square regular tiling (Weisstein, 2021). The size of the graph is determined by the number of nodes along its height, n, and the number of nodes along its width, m. From Figure 3B, n   =   3 and m   =   3 , and the graph can be described as a “3 × 3 square lattice,” consisting of a total of 9 nodes and 12 edges.

To specify the location of a node, the graph can be considered as a coordinate system, with the coordinate (0, 0) representing the bottom-left node. If a node is located at coordinate ( i , j ) , it is given the number n ( i   − 1 )   +   j   − 1 , where, as before, n represents the total number of nodes along the width of the graph.

In other words, the bottom-left node is assigned to be the node number 0, and the node number counts upwards from left to right along each row. When the rightmost node of a row is reached, the next node counted is the leftmost node of the row directly above. The top-rightmost node is the highest-numbered, with node number mn − 1. This numbering system, applied to a 3 × 4 square lattice graph, is depicted in Figure 4. Individual edges/converters can be referenced by the two nodes adjacent to them. For instance, “edge 2–3” or “converter 2–3” can be equivalently used to reference the H-bridge converter connecting node 2 and node 3.

A triangular lattice graph is formed by a regular tiling of equilateral triangles. However, the rows of a triangular lattice can be shifted, as shown in Figure 5, so that the lattice lies on an m × n square arrangement of nodes. Thus, it is evident that an m × n triangular lattice is very similar to an m × n square lattice.

There are two embodiments of triangular lattices, which will be referred to as “type 1” and “type 2”, respectively. A type 1 triangular lattice is the one whose bottom left node has exactly three adjacent nodes, as shown in Figure 5A. In a type 2 triangular lattice, the bottom left node has exactly two adjacent nodes, as shown in Figure 5B.

The nodes of a hexagonal lattice graph can also be shifted to lie in an m × n square arrangement, as shown in Figure 6. The hexagonal lattice takes on a “bricklaying” pattern. Vertical edges are connected in the same way as in a square lattice. However, a node is never connected horizontally to the right if there is already a node connected to its left. Furthermore, if a row begins with a pair of connected nodes, then the row above it must begin with a pair of unconnected nodes.

There are also two embodiments of hexagonal lattices. Type 1 has its bottom left node connected to exactly two other nodes, while type 2 has its bottom left node connected to exactly one other node (see Figure 6). In other words, the bottom row of a type 1 lattice begins with two connected nodes, while the bottom row of a type 2 lattice begins with two unconnected nodes.

This paper has discussed lattice power grids based on the three regular tilings: square, triangular, and hexagonal. However, the models and algorithms detailed in this paper are not limited to these three lattice types. As discussed later in Generalizing the Proposed Algorithms for Various Lattice Structures section, through the use of adjacency matrices, all of these concepts can be fully extended to any grid topology that is based on a simple, undirected graph. Several other lattice converter topologies have been proposed by Fang (2021b). In two dimensions, this includes the eight Archimedean tilings in addition to the three regular tilings. In three dimensions, novel lattice converters based on polyhedral tilings, or honeycombs, have been investigated as well. These include the cubic honeycomb lattice converter, as well as 28 lattice converter topologies based on Archimedean honeycombs (Fang, 2021b). Because these aforementioned topologies can all be represented using simple, undirected graphs and their adjacency matrices, the concepts discussed in this paper can be fully extended to them.

The goal is to create control and optimization algorithms that can satisfy a set of input parameters. Each node in a lattice power grid can be viewed as an I/O terminal. The algorithm should be able to accept two arbitrary nodes and create a desired voltage difference along a path between them. To carry an enough current between two nodes, it is sometimes necessary to create two or more paths in parallel between them, allowing for current sharing between the H-bridge voltage sources along the paths.

These are the two main objectives of any grid state outputted by the algorithm: achieving a desired voltage between two nodes and creating a desired number of parallel paths between them. Figure 7 depicts a grid state of a 4 × 4 square lattice power grid, where node 2 is the “start” node and node 13 is the “destination” node. Edges colored in blue represent H-bridge converters in the bypass mode (shorted), and edges in red represent converters in the ON state, either outputting +V_dc or −V_dc. Uncolored edges represent converters acting as an open circuit. In the grid state shown in Figure 7, there is a voltage difference of +3V_dc between the start and destination nodes, and three paralleled paths between them.

All converters that are outputting voltages should be creating a voltage increase along its path in the direction from start to destination. For example, along the leftmost path of Figure 7, there should be a voltage increase of V_dc from node 2 to node 1, another from node 1 to node 0, and another from node 0 to node 4, creating a total voltage increase of +3V_dc along the path.

A new convention can be introduced here to determine whether an individual H-bridge converter is in the positive output state or the negative output state. If the converter creates a voltage increase from the lower-numbered node to the higher-numbered node, it is in the positive output state. On the other hand, if the converter creates a voltage increase from the higher-numbered node to the lower-numbered node, it is in state 2. For instance, in Figure 7, converter 1–2 is outputting −V_dc, while converter 2–3 is outputting + V_dc.

Another objective can be considered when changing from one state to another. There may be multiple different states that fulfill the same parameters. If the lattice grid is in an initial state, and it is desirable to change states to fulfill a different set of parameters, there are often several possible end states to select from. The most efficient way to perform this change is by selecting the end state that requires the fewest number of individual converter-level state changes from the initial grid state. This is the final objective of the optimization algorithm.

In the beginning, the lattice graph is implemented through a class called Graph. This class contains two main attributes: an integer representing the number of nodes in the graph and a dictionary indicating node adjacencies. If a graph contains v nodes, then its dictionary includes v keys 0 ,   1 ,   ... ,   v   −   1 . The value corresponding to key x is a list containing all nodes that are adjacent to node x in the graph.

The Graph class also contains the function addEdge ( a ,   b ) , which appends node b to the list corresponding to key a in the dictionary, indicating that node a is adjacent to node b. A graph g consisting of v nodes can be initialized using the statement g   =  Graph ( g ) , creating a graph of v unconnected nodes, which can then be connected using addEdge.

To create an m   x   n square lattice from an initially unconnected graph g, the createGrid function iterates through all nodes in the graph. For a node with position (i, j) and node number x, createGrid uses addEdge to connect it with the node to its right, if one exists, and the node above, if one exists. If j   +   1   ≤   n , then node x   +   1 (the node to the right) is connected to x. If i   +   1   ≤   m , then node x + n (the node above) is connected to x. This process is demonstrated in Figure 8 for a 2 × 3 square lattice graph. After iterating through all nodes in the graph, the result is an m   ×   n square lattice grid.

The pathfinding component of the control and optimization algorithms will address the desired voltage difference parameter. The inputs to this algorithm are the desired dimensions m and n of the square lattice graph, the start and destination node numbers, and the desired voltage difference to be created between them.

Conceptually, to create a voltage difference between two nodes of +kV_dc, where k is an integer, a path of length k or greater must be found between the nodes. If a path has length l, where l   ≥   k , the first k edges along the path can each create a voltage increase of V_dc in the direction from start to destination, while the remaining l   −   k edges in the path can be bypassed. It can be noted that these “paths” consist of H-bridge converters connected in series; this is essentially a cascaded-bridge multilevel converter.

Two caveats will be addressed here; firstly, only integer values of k will be considered, as non-integer multiples of V_dc can be achieved through pulse-wave modulation. Secondly, it is not necessarily required that the first k edges in the path output voltage and the rest remain bypassed. It would be a valid solution to distribute the l − k bypassed edges in any possible way throughout the path. However, for the sake of simplicity and for preserving the efficiency of the algorithm, the only solutions that will be considered are those where all bypassed edges are located towards the end of the path, near the destination node.

The pathfinding algorithm itself, named findPaths, utilizes Depth-First Search (DFS) of a graph to search for viable paths (Goodrich and Tamassia, 2001; Yadav, 2021a; Yadav, 2021b). While traversing a graph, it is possible to visit the same node twice, which is not possible in a binary search tree. This must be avoided during DFS, so the algorithm also tracks which nodes have been visited (Yadav, 2021a). As the algorithm traverses the graph, visited nodes will be marked as such and will not be revisited. While the algorithm is backtracking, nodes removed from the path will again be marked as “unvisited,” allowing for new paths to be found.

This DFS algorithm traverses all possible paths through the graph originating from the start node. The other two input parameters to findPaths are the destination node number and the desired voltage difference k. With every edge traversal, findPaths checks if the current visited node is the same as the destination node. If this is the case, findPaths then checks whether this path from start to destination is of length k or greater. If both conditions are met, then the algorithm has found a viable path, which is stored in a list of lists. When the DFS algorithm has finished running, this list of lists contains all viable paths from start to destination and is returned by findPaths.

Suppose the inputs to findPaths are m = 2 , n = 3 , start node 0, destination node 5, and k = 3 . Then the output of findPaths is the following list of lists: { [ 0,  1 ,  2 ,  5 ] ,  [ 0,  1 ,  4 ,  5 ] ,    [ 0,  3 ,  4 ,  1 ,  2 ,  5 ] ,  [ 0,  3 ,  4 ,  5 ] }

Thus, there are four viable paths that meet the desired parameters in this example: three paths of length 3 and one path of length 5.

The parallel paths component of the control and optimization algorithms, called currentPaths, will meet the requirement of current sharing. As real-world power converters are non-ideal and are limited by current ratings, it is often necessary to share current by connecting voltage sources in parallel. In the case of lattice grids, the amount of available current depends on the number of paralleled paths between the source and destination nodes.

For two paths to be considered parallel, they must meet at the start and destination nodes and cannot share any edges. Intersections between two or more paths are possible; however, at the point of intersection, all paths must yield the same voltage to avoid a conflict. Figure 7 depicts an example of a 4   ×   4 lattice with three paralleled paths between node 3 and node 12.

The algorithm works as follows. Given an m   ×   n square lattice graph, a pair of start/destination nodes, and a desired voltage difference, all viable paths can be determined by the pathfinding algorithm findPaths as described previously. These viable paths are outputted in the form of a list of lists, with each list containing a path. In each of these lists, the first element is the starting node, and the final element is the destination node.

Suppose that p is the desired number of paralleled paths. Then currentPaths arranges viable paths in permutations of size p. For each permutation, the algorithm iterates through each path contained in the permutation. The voltage of each node in the lattice is tracked and updated by the algorithm as it iterates through the paths. If a voltage conflict is detected between two paths in a permutation, then it is considered an invalid intersection and the permutation is discarded.

Furthermore, two parallel paths cannot share an edge. Thus, the algorithm also tracks which edges are occupied using an ( m   x   n )   x   ( m   x   n ) matrix similar to an adjacency matrix. This matrix is initially all zeros, but elements are replaced with a value of 1 when a path traverses the associated edge. If another path attempts to traverse this edge, then an edge conflict arises, and the permutation is discarded. The remaining path permutations are thus considered valid and are returned by currentPaths.

Recall the example output from Pathfinding Algorithm section given by findPaths for a 2 × 3 square lattice graph with start node 0, destination node 5, and desired voltage difference 3: [ [ 0,  1 ,  2 ,  5 ] ,   [ 0,  1 ,  4 ,  5 ] , [ 0,  3 ,  4 ,  1 ,  2 ,  5 ] , [ 0,  3 ,  4 ,  5 ] ]

Now, suppose that two parallel paths are desired to provide current sharing. Then, the four viable paths are placed in every possible permutation of size two, of which there are six:

1) [[0, 1, 2, 5], [0, 1, 4, 5]].

Of these six permutations, the second and fourth can be discarded due to voltage. All except the third can also be discarded due to edge conflicts (e.g., edge 0–1 in permutation 1). The algorithm concludes that the two paths [0, 1, 2, 5] and [0, 3, 4, 5] from permutation 3 are in fact parallel and represent the only valid solution to the given parameters as no conflicts arose.

The algorithm in its current version assumes that paralleled paths start and end at the same nodes. Thus, the maximum number of paralleled paths is limited by the number of nodes adjacent to the start or destination nodes. The maximum number of paralleled paths can be theoretically increased through edge contraction, in which the start/destination nodes can be combined with neighboring nodes via short circuit (Belloch, 2012), essentially forming a “supernode” that can accommodate a greater number of paralleled paths. While not implemented in the current version of the algorithm, edge contraction represents a possible area for further exploration.

The leastChanges algorithm deals with time-variant state changes of grid-forming converters. Assuming that the lattice power grid is in some initial state, it is then required to change the state to fulfill new objectives, then the most efficient way to do so is to select the end state that requires the smallest number of individual converter-level state changes, thus minimizing switching actions. In other words, out of all possible end states that fulfill the new objectives, the most efficient end state is the one that is the “most similar” to the initial state.

The “similarity” between two grid states can be compared using adjacency matrices. A grid consisting of v nodes will have an associated adjacency matrix of size v × v. In graph theory, adjacency matrices typically allow for two states: 0, indicating a pair of non-adjacent nodes, or 1, indicating an adjacency. However, as described in Fundamentals of Lattice Power Grids section, H-bridge converters can yield four possible states. Thus, the adjacency matrices introduced here also have four possible values for each element. 0 represents an open circuit, 1 and −1 represent an H-bridge converter outputting + V_dc and −V_dc, respectively, and 0.01 represents the bypass state, with the value chosen to represent a negligible voltage difference.

This adjacency matrix indicates the states of each H-bridge converter and will be referred to as the “path matrix.” This is meant to distinguish from the “graph matrix,” a separate adjacency matrix that is discussed later in Generalizing the Proposed Algorithms for Various Lattice Structures section. An example of the path matrix is depicted in Figure 9, where a grid state of a 3 × 3 lattice is shown in Figure 9A and its associated path matrix P is shown in Figure 9B.

Each converter-level state change is associated with two changes in the path matrix (changing the state of edge a-b will change elements P _ab and P _ba in path matrix P). The leastChanges algorithm thus obtains the path matrix of the initial state, along with the path matrices of all viable path permutations outputted by currentPaths. The most efficient end state is the one whose path matrix has the fewest number of differences from the initial path matrix. If there are d differences between the initial and end path matrices, then d/2 converter state changes must have occurred.

Suppose that the state depicted in Figure 9A is taken to be the initial state. Then suppose that a set of new requirements is desired: +4V_dc voltage difference, only one current path, start node at node 0, and destination node at node 8. The end state selected by leastChanges and its associated path matrix are shown in Figure 10.

Out of all viable end states that fulfill the desired parameters, the state shown in Figure 10A is the one that requires the smallest number of converter-level state changes from the initial state. Seven converter-level state changes are required in this example (Note that edges 1–4 and 4–5 flipped in polarity).

The components of the proposed control and optimizations algorithm can now be integrated into one. The final optimization algorithm runs on a while loop. On the first loop, the user is prompted for the dimensions m, n of the square lattice, and the graph is created using createGrid. The initial state on the first loop has all converters turned OFF, so all elements in its path matrix are filled with 0. The user then inputs desired specifications for the end state: start, destination, target voltage, and number of parallel paths. The algorithm calls findPaths and currentPaths to identify all path permutations that fulfill the parameters. These permutations are inputted into leastChanges, which identifies the most efficient end state.

The previous end state then becomes the new initial state. The algorithm can prompt the user to input new parameters, and the process can continue indefinitely. On each loop, the algorithm outputs the following: the path permutation of the end state, the path matrix of the end state, and the number of converter-level state changes from the initial state. The end state is then plotted using the networkx Python package.

To allow for the creation of arbitrary graphs, the “graph matrix” is introduced here. The graph matrix is another adjacency matrix that indicates which nodes are connected by H-bridge converters (edges). For a graph containing v nodes, its graph matrix will contain v × v elements. If an edge exists between nodes a and b, then element G _ab and G _ba will be filled with 1. Otherwise, it will be filled with 0. This is distinct from the path matrix described earlier, which indicates the state of each converter (+V_dc, −V_dc, shorted, or OFF).

The function used to create the desired graph matrix is called createGM (rather than createGrid). A graph matrix can be used to create a Graph object by iterating through each element of the matrix and using the addEdge function to connect nodes as directed. The graph matrix outputted by createGM is passed into findPaths, which uses it to create a Graph object, and the rest of the algorithm works exactly as described in Components of Control and Optimization Algorithms for Square Lattice Grids section.

Any simple, undirected graph can be created using graph matrices. Besides square lattice graphs, there exist two other types of lattice graphs: triangular and hexagonal. Creating a Triangular Lattice and Creating a Hexagonal Lattice sections explain how graph matrices can be used to generate triangular and hexagonal lattice graphs.

The graph matrix for the square lattice graph is generated in exactly the same way as described in Creating a Square Lattice Graph section, except by filling in the elements of a graph matrix instead of directly using the addEdge function.

The process starts with an (m × n) × (m × n) matrix G, consisting of all zeroes. The createGM function iterates through all nodes in the graph. For a node with position (i, j) and node number x   =   n ( i   –   1 )   +   j   −   1 , elements G _x,x+n and G _x+n,x are flipped to 1 if i   +   1   ≤   m , and elements G _x,x+1 and G _x+1,x are flipped to 1 if j   +   1   ≤   n . This connects the node with the node to its right, if one exists, and the node directly above, if one exists. Upon repeating this process for every node in the lattice, createGM outputs the graph matrix for an m x n square lattice graph.

Recall that a triangular lattice simply consists of diagonal connections added to a square lattice (see Figure 5). Thus, the procedure for forming a graph matrix for a triangular lattice graph matrix is the same as the procedure for a square lattice graph, with the addition of diagonal connections. For a type 1 triangular lattice, each node x is connected to the node directly to its top right if one exists. In other words, for a node with position (i, j) and node number x   =   n ( i   –   1 )   +   j   –   1 , node, graph matrix elements G _x,x+n+1 and G _x+n+1,x are flipped to 1 if i   +   1   ≤   m and j   +   1   ≤   1 . This connects node x with node x + n + 1. Horizontal and vertical connections are handled as they were for a square lattice.

For a type 2 triangular lattice, each node x is connected to the node directly to its top left if one exists. In other words, graph matrix elements G _x,x+n−1 and G _x+n−1,x are flipped to 1 if i   +   1   ≤   m and j   −   1   ≥   0 . This connects node x with node x   +   n   −   1 .

Upon repeating this process for every node in the lattice, createGM outputs the graph matrix for an m × n triangular lattice graph (see Figure 11).

Recall that a hexagonal lattice can also be placed on a square arrangement of nodes (see Figure 6), forming a “brick” pattern. In this pattern, pairs of horizontally adjacent nodes alternate between being connected and unconnected across the rows and columns of the lattice.

This pattern is achieved through the addition of a Boolean value named connect, which determines whether the current node will be connected to the right. For a type 1 lattice, when createGM reaches the first node in any row i, connect is set to FALSE if the row is even ( i   %   2   =   0 ), or set to TRUE if the row is odd ( i   %   2   =   1 ). Row 1 is considered to be the bottom row. Then, as createGM iterates across the row, the value of connect flips with each iteration. These alternating horizontal connections form the “brick” pattern seen in Figure 6.

Upon repeating this process for every node in the lattice, createGM outputs the graph matrix for an m x n hexagonal lattice graph (see Figure 12).

The final version of createGM essentially consists of six ‘if’ statements, one for each potential type of graph. If the user inputs “G” for “general,” createGM prompts the user to input the desired graph matrix row by row, allowing for any arbitrary graph. The user inputs “S” for a square lattice, “T1” or “T2” for a type 1 or type 2 triangular lattice, and “H1” or “H2” for a type 1 or type 2 hexagonal lattice. If the user inputs one of these lattice types, createGM will also prompt the user to input dimensions m and n of the lattice. The final output of createGM is the desired graph matrix.

The integrated optimization algorithm is the same as described in Components of Control and Optimization Algorithms for Square Lattice Grids section, except createGrid is replaced with createGM. The graph outputted by createGM is passed into findPaths, where all viable paths fulfilling the desired parameters are outputted. currentPaths then finds viable permutations of parallel paths. leastChanges determines which permutation requires the smallest number of converter-level changes from the initial state. This permutation is then printed and drawn. A flowchart of the overall control and optimization algorithms is depicted in Figure 13.

The lattice grid was simulated under the MATLAB Simulink/SimScape environment. The H-bridge converters were built with the “Full-Bridge Converter” block in SimScape (Mathworks, 2021). In the converter subsystem, the Full-Bridge Converter block is connected to a 1 kV DC voltage source for simplicity. It is given an on-state resistance of 10^–3 Ω and a snubber resistance of 10⁶ Ω, as well as an infinite snubber capacitance. A control signal entering the gating port consists of a 1 × 4 array controlling the four semiconductor switches in the converter (Mathworks, 2021). The matrices [0 1 1 0] and [1 0 0 1] correspond to the positive and negative ON-states, respectively. The matrix [1 0 1 0] (or [0 1 0 1]) corresponds to the bypass state, while [0 0 0 0] corresponds to the OFF-state.

Figure 14 shows the complete simulated model of a 3 × 4 square lattice power grid. In all, this model contains 17 H-bridge converter submodules, along with 17 × 4 gating signals to control them. As a 3 × 4 lattice contains 12 nodes, the path adjacency matrix (PAM) representing any given grid state will be a 12 × 12 matrix. Thus, the controller block is a MATLAB function block which accepts a 12 × 12 matrix as the input and demultiplexes it into 17 × 4 output gating signals. The grid state can then be set by inputting the appropriate path adjacency matrix into the controller block.

We inputted the following parameters into the control and optimization algorithms:

Enter the Desired Lattice Type: S

Enter the height m of the grid: 3

Enter the width n of the grid: 4

Enter the starting node number: 0

Enter the destination node number: 11

Enter the desired voltage difference: 3

Enter the desired number of paralleled paths: 1

These parameters returned a grid state and path adjacency matrix shown. This path adjacency matrix was placed into the model. An RLC load was connected between nodes 0 and 11 of the model, with a resistance of 5 Ω, an inductance of 10 mH. Voltage and current measurement blocks were connected accordingly as well (see Figure 14). (Note: In Figure 14, submodule blocks were colored in manually to indicate converter states).

The current and voltage measurements after running the simulation are shown in Figure 15. The results are as desired and expected, with the voltage difference between nodes 0 and 11 being +3 kV and the current approaching 0.6 kA by Ohm’s law. As there is only one path, the current rating of each submodule must be at least 0.6 kA for this grid state to be possible.

When measured between nodes 0 and 3, the voltage difference was found to be +3 kV. When measured between nodes 3 and 11, the voltage difference was found to be 0 V. This agrees with expectations, as submodules between nodes 3 and 11 are in the bypass state and do not output voltage.