Excellent material characteristics of WBG devices enable the high efficiency, high frequency and high power density design of power converters. They are commercially available in both discrete and module packages (CREE, 2021b; Infineon, 2021a; Infineon, 2021b; Rohm, 2021). Discrete and module packages are commonly used in low and high power applications, respectively. In medium power applications such as an electric vehicle (EV), both packages can be employed (Bertelshofer et al., 2019; Lu, 2020; Infineon, 2021c). Module packages have advantages of high current ratings and low package inductance (Chen et al., 2017; Hou et al., 2020; Lee et al., 2020). However, they are expensive and lack design flexibility (Jahns and Dai, 2017; Bertelshofer et al., 2019; Lu, 2020). The discrete package features a cost-optimized solution and enables quick prototyping of available convert designs at different power levels (Bertelshofer et al., 2019; Lee et al., 2020). The flexibility facilitates the converter manufacturers to fulfill specific requirements. For instant, the discrete package is a good fit for the data center uninterruptible power supply (UPS) (Infineon, 2021c) and integrated motor drive inverters as it assists full integration (Jahns and Dai, 2017). Generally, for the same chip size, the available cooling area is larger in discrete package compared with module package as illustrated in Figure 1, which enables the device to better handle the fleeting overloading condition and can simplify the thermal design (Infineon, 2021c). With the advancements in packaging technology, new discrete packages such as TO-247PLUS offer higher power ratings and better thermal performance thanks to the bigger backside active thermal pad (Infineon, 2017; Infineon, 2021b; Sobe et al., 2020; IXYS, 2021). Finally, the discrete package is offered by more number of suppliers and it enables the designers to choose their preferred supplier based on price, region and customer support. The simple manufacturing process of discrete packages encourages the second sourcing strategies; thus, promoting the competition and as result, the price of discrete packages is expected to drop faster than that of module package. A 150 kW EV inverter with parallel-connected discrete (TO-247) SiC MOSFETs achieved a longer lifetime and similar power density compared to the Si module package (Bertelshofer et al., 2019). In addition, Tesla has also used discrete devices in parallel to push up the current ratings to achieve a cost-effective solution for EV inverters (Jahns and Dai, 2017; Jahns and Dai, 2018).

The discrete packages own the advantages of flexibility, scalability and reduced cost; though, challenges of severe switching oscillations and limited current capacity are associated with them. This review provides a comprehensive and in-depth overview of advanced performance improvement strategies to overcome these challenges.

The high-frequency operation of WBG devices enables higher power density design by reducing the size of passive components. However, fast switching speed inevitably increases di/dt and dv/dt, inducing switching oscillations. The dv/dt of Silicon (Si) devices is typically around 3 V/ns (Ji et al., 2017) whereas that of Silicon Carbide (SiC) MOSFETs and Gallium Nitride (GaN) HEMT can reach 50 V/ns (Ji et al., 2017) and 80 V/ns (Hughes et al., 2012), respectively. Besides, low stray capacitance and the smaller R _DSon of WBG devices aggravate the oscillations (Zhang W. et al., 2014; Huang et al., 2017; Wang et al., 2018). Oscillations get more severe in the discrete package due to the high parasitic inductance of the package and printed circuit board (PCB). These oscillations have adverse effects on the convert performance such as additional power losses (Abou-Alfotouh et al., 2006; Chen, 2009; Mermet-Guyennet et al., 2012; Chen, 2014; Nayak et al., 2014; Dong et al., 2015; Jahdi et al., 2015; Liang et al., 2019; Meng et al., 2019), increased EMI noise (Gong et al., 2013; Tsai et al., 2013; Zare et al., 2015; Fang et al., 2017; Zhang et al., 2019; Zhang and Wang, 2020), shoot through (Elbanhawy, 2005; Watanabe and Itoh, 2011; Xu et al., 2013; Yanagi et al., 2014; Zhang Z. et al., 2014; Ishibashi et al., 2015; Yin et al., 2016; Wang et al., 2018) and overshoots in current and voltage (Gamand et al., 2012; Joko et al., 2015; Ando and Wada, 2017; Liang et al., 2017).

High-power applications require high current ratings switching devices; however, the maximum current of a commercially available discrete SiC MOSFET is limited to 115A (CREE, 2021b; Infineon, 2021a; Rohm, 2021). To increase the current ratings, discrete devices are usually used in parallel for high-power applications (Bertelshofer et al., 2019). Due to a mismatch in the parameters of the devices (Wang G. et al., 2014; Ke et al., 2018; Zhao et al., 2021a; Zhao et al., 2021b) and asymmetrical layout design (Li et al., 2014a; Tiwari et al., 2015; La Mantia et al., 2017), the current distribution among parallel-connected discrete devices is uneven, leading to imbalanced power loss distribution, uneven temperature rise and risk of device thermal runaway.

Recently, several studies have been reported to address above mentioned issues, but a comprehensive overview of the discrete package is lacking. Previously published survey articles focus on different aspects (Millán et al., 2014; Wang and Zhang, 2016; She et al., 2017); analyze the performance and applications of WBG devices. Commercialization, design challenges and fabrication methods are discussed in Jones et al. (2016) and Zhao S. et al. (2021), active driving solutions for module packages are discussed in Zhao S. et al. (2021), packaging technology and progress of module packages are presented (Hou et al., 2020; Lee et al., 2020; Alizadeh and Alan Mantooth, 2021). A systematic overview of the discrete package offering performance improvement strategies is required to unleash its potential. This survey comprehends switching oscillations and uneven current distribution issues of discrete packages. Oscillations are classified in terms of drain to source voltage (V _ds ) and gate to source voltage (V _gs ) and the underlying oscillation mechanism is explored in depth. In addition, the uneven current distribution is categorized into static current imbalance and dynamic current imbalance. Root causes and adverse effects of the current imbalance are also included. Furthermore, stray parameters extraction techniques are also discussed. In the end, the latest oscillation attenuation methods and current imbalance solutions are systematically summarized which can assist readers to fully leverage the benefits of the discrete packages.

Gate to source voltage (V _gs ) oscillation may cause false action like false turn-on or false triggering as shown in Figure 2A. Both of them may lead to a shoot-through issue. The shoot-through current deteriorates the performance, increases switching losses, and can even damage the devices (Elbanhawy, 2005; Watanabe and Itoh, 2011; Xu et al., 2013; Yanagi et al., 2014; Zhang Z. et al., 2014; Ishibashi et al., 2015; Fan et al., 2016; Yin et al., 2016; Wang et al., 2018). The difference between false turn-on and false triggering lies in single and repeated trigger action. The false turn-on is mainly related with the high dν/dt and di/dt in WBG devices (Khanna et al., 2013; Wang and Chung, 2014; Yanagi et al., 2014; Ishibashi et al., 2015; Jahdi et al., 2015; Wang et al., 2018; Li R. et al., 2019). When one of two MOSFETs in a phase leg configuration turns on, a fast-rising voltage appears across the off-state MOSFET, as shown in Figure 4. As a result, a current flow in the gate loop through C _gd causing a voltage drop. If the voltage drop is higher than the device threshold voltage, a false turn-on event would occur leading to shoot-through. Typically, the duration for a false turn-on is between 10 and 100 nsec (Yin et al., 2016) and the value of current can reach up to 150 A (Yanagi et al., 2014). As shown in Figure 3A, L _s stays in both gate loop and power loop. It indicates that a negative gate voltage would be introduced by high di/dt from power loop which can worsen the oscillation leading to false triggering. False triggering is reported in both SiC (Lemmon et al., 2013, 2014; Sugihara et al., 2017) and GaN (Umetani et al., 2016, 2019; Matsumoto et al., 2017) devices, though, the latter one is more susceptible to false triggering owing to its low threshold voltage. A comprehensive analysis of false triggering oscillations is provided in Umetani et al. (2016) and it is concluded that in order to avoid the false triggering oscillation the resonance frequency of the power loop and that of the gate loop should be decoupled. Besides, an optimum device selection and proper circuit layout design are important for depressing the gate oscillations by minimizing C _gd and L _s .

Static current imbalance is due to the variation in R _DSon of parallel-connected devices. During the on state, MOSFETs behave like a small resistor and a group of MOSFETs connected in parallel has the advantage of reduced resistance current path. Due to R _DSon variation, the device with the lowest resistance conducts more current and has relatively higher conduction losses, as a result, its resistance increases. In Si MOSFETs, owing to the positive temperature coefficient (PTC) of R _DSon, the static current imbalance naturally gets reduced (Xue et al., 2013; Mao et al., 2017a; Mukunoki and Horiguchi, 2018; Zeng et al., 2020). As shown in Figure 5E, the TO-247 package of Si, SiC and GaN MOSFETs with similar ratings have been tested. It is concluded that when the temperature is raised from 25°C to 175°C, the R _DSon of Si, SiC and GaN increases by 3×, 1.5× and 2×, respectively. Hence, the intrinsic current sharing capability of WBG MOSFETs is not as prominent as that of Si counterparts (Wang G. et al., 2014; Xue et al., 2014a; Ke et al., 2018; Zeng et al., 2020; Zhao et al., 2021a; Zhao et al., 2021b). In addition, the value of gate to source voltage (V _gs ) also influences the R _DSon (Wang G. et al., 2014).

The dynamic current of a device depends on its threshold voltage (V _th), gate to source voltage (V _gs ) and transconductance (g _fs ) as depicted in Eq. 1. Among parallel-connected devices, the device with lower V _th or higher g _fs conducts more dynamic current leading to dynamic current unbalance. Furthermore, dynamic current imbalance increases with a rise in temperature due to the negative temperature coefficient (NTC) of threshold voltage (V _th). At higher frequency, even a slight discrepancy in L _s of parallel-connected MOSFETs will induce negative feedback to gate voltage as revealed in Eq. 2, and the change in V _gs will directly impact the drain current as shown in Eq. 1. I d = g f s ( v g s − V t h ) (1) v g s = V d r i v e r − i g R g − L s d i s d t (2)

Dynamic current imbalance leads to unequal distribution of switching losses among parallel connected devices. The impact on switching losses variation from the current imbalance is illustrated in Figures 5A–D (Timms, 2018). It shows that the dynamic current and switching losses distribution are mainly affected by the V _th and L _s . As demonstrated in Figure 5F (Timms, 2018), a lower L _s means a faster switching speed. In addition, a lower V _th means faster turns on but slower turns off. Hence, matching the V _th and L _s of parallel-connected devices is crucial to suppress the dynamic current imbalance.

In summary, the prominent root cause of static current imbalance is R _DSon whereas the mismatch in V _th, L _s or g _fs instigates the dynamic current imbalance. The adverse effects of the current imbalance include uneven power loss distribution, increased stress to a single device, higher current overshoots, uneven temperature rise and all contribute to reduced reliability.

The external gate resistor plays a critical role in the device’s performance. The dv/dt or di/dt of a device can be decreased by increasing the gate resistor (R _g ), leading to a reduced oscillation and overshoots (Liu et al., 2016b) at the cost of increased switching losses. A detailed gate resistor effect demonstration is shown in Liu et al. (2018b), where an additional 10 Ω gate resistor brings a reduction of about 15 and 4% in voltage overshoot and oscillation duration, respectively. In another aspect, a significant increase in turn-on and turn-off times is resulted and the turn-on energy (E _on ) and turn-off energy (E _off ) get increased by 64 and 80%, respectively. Gate resistor also impacts the false triggering oscillation and parasitic ringing, as reported in Gafford et al. (2013), Li and Munk-Nielsen (2014a), and Liu et al. (2018b). The gate resistor can be viewed as the tradeoff between switching losses and switching oscillations. To determine an optimum value of R _g , equivalent circuits, the analysis and validation are provided in Chen and Amaro (2012), Liu et al. (2016a), and Paredes et al. (2017).

Adjustment of gate resistance can be viewed as a simple and specified way in gate driver to mitigate oscillations. Many well-designed gate drivers for oscillation and crosstalk depression are reported in the literature (Paredes Camacho et al., 2017; Paredes et al., 2017; Zhang et al., 2017). Gate drivers can be categorized as open loop gate drivers, active gate drivers and multi-level gate drivers.

To suppress the oscillation, the large gate resistance increases the energy losses and the active gate driver approach demands complex feedback control. RC snubber offers reduced cost and complexity compared with the active gate driver and slightly less energy losses compared with the gate resistance method. RC snubber is a widely adopted solution for oscillation attenuation (McMurray, 1972; Josifović et al., 2011; Josifovic et al., 2012; Salem and Wood, 2014; Vaculik, 2014; Joko et al., 2015; Liu et al., 2016a; Liu et al., 2016b; Torsæter et al., 2016; Chen et al., 2021; Yang et al., 2021). Choosing optimum values of snubber for effective oscillation suppression is essential. An efficient way to design these parameters is to simplify the switching circuit into an equivalent RLC circuit incorporating all circuit parasitic. Then switching oscillations can be modeled using the RLC equivalent circuit and theoretical analysis of models can provide the guidelines for designing RC snubber. The equivalent RLC circuit of DPT including snubber is shown in Figure 8A. Snubber design methods can be categorized into second order, third order and higher order. Compared with the second order method, third order and higher order design methods enable better oscillation mitigation in both V _ds and V _gs as depicted in Figures 8B,D at the cost of increased design complexity (Chen et al., 2020). Detailed guidelines to design snubber using second order approach are provided in Josifović et al. (2011), Josifovic et al. (2012), Salem and Wood (2014), Vaculik (2014), Joko et al. (2015), and Torsæter et al. (2016) and those for third order and higher order methods are discussed in Yatsugi et al. (2018) and Chen et al. (2020).

Switching oscillation and switching losses can also be mitigated by implementing either the zero voltage switching or zero current switching or both (Hua et al., 1994; Watson et al., 1996; Lai, 1997; Tang et al., 1998; Zhang et al., 2007; Chen et al., 2013b; Chen et al., 2013c; Ahmed et al., 2017). Usually, an additional capacitor/inductor or their combination is implemented in the topology to realize resonance for achieving soft switching. Researchers (Ahmed et al., 2017) illustrated that soft switching can significantly reduce the oscillation with 86% drop in dv/dt. Soft switching also has certain drawbacks, such as increasing part count and making the control system more complex (Toshiba, 2019). Therefore, it is important to determine if soft switching is suitable for the required application. Since soft switching is valuable to minimize diode recovery loss and transformer leakage inductance loss (Toshiba, 2019), it is widely adopted in isolated dc-dc converters such as LLC, CLLC and Flyback converts (Hua et al., 1994; Watson et al., 1996; Lai, 1997; Tang et al., 1998; Zhang et al., 2007; Lu et al., 2021; Spiazzi and Buso, 2021).

Ferrite beads are effective to mitigate the oscillation as reported in Dodge (2004), Josifović et al. (2011), Josifovic et al. (2012), Zhao et al. (2017), and Liu et al. (2018b). These beads work based on Faraday’s law; when a high frequency oscillation passes through the ferrite bead, a back emf is induced in the core of the bead that attenuates the oscillation. Ferrite bead can be employed in the power loop to reduce oscillation in V _ds or in the gate loop to reduce oscillation in the V _gs . A ferrite bead implemented in the power loop is illustrated in Figure 9A. The characteristics graph of a ferrite bead is shown in Figure 9B (Liu et al., 2018b). For effective oscillation mitigation, the undesired frequencies must be in the resistive band of the ferrite bead. The oscillation frequency (f _osc ) can be determined using Eq. 3, where C _eq is equivalent stray capacitance and the sum of ferrite beat inductance along with equivalent circuit’s inductance is represented by L _eq . In addition, the damping coefficient (m) can be calculated using Eq. 4 where the resistive impedance of the bead is denoted by R _seq . As ferrite bead’s inductance and capacitance are frequency dependent, the following conditions must be satisfied to achieve effective oscillation suppression. f o s c i l l a t i o n = 1 2 π C e q × L e q (3) m = R s e q / [ 2 × ( L e q C e q ) ] (4)

1) The damping coefficient must be greater than one (m > 1), for selected values of resistor and inductor of the bead.

As the characteristics of ferrite beads vary with load current, therefore, impedance vs load current curves should be referred to select the right ferrite bead. Figure 9C reveals the influence of ferrite bead on voltage oscillation of SiC MOSFET (Kim et al., 2017). Ferrite beads are effective for EMI reduction and at 15 MHz oscillation frequency, a noise reduction of 15 dB has been achieved in a SiC-based boost (Kim et al., 2017). By employing ferrite bead, 3.8% reduction in voltage overshoot and 78.45% reduction in oscillation duration of SiC MOSFET were achieved by Liu et al. (2018b). No matter how precisely parameters of ferrite are selected, a small amount of dc resistance is inevitable, which causes a slight increase in the conduction losses. Comprehensive design guidelines for ferrite beads can be found in Josifović et al. (2011), Josifovic et al. (2012), and Liu et al. (2018b).

To summarize, careful selection of a device with low package inductance and kelvin source can alleviate the oscillation. In addition, an optimized PCB layout offers reduced oscillation by diminishing the power loop and gate loop inductances. Increasing external gate resistance reduces the oscillation but slows down the switching speed leading to increased switching losses. Active gate driver can reduce the overshoots and cross-talk by controlling the di/dt and dv/dt, but increases the circuit cost and design complexity. The RC snubber method offers effective oscillation mitigation but slightly increases switching losses. Ferrite beads perform better to suppress high-frequency oscillations at the cost of slightly increased conduction loss. All oscillation mitigation methods have their pros and cons that are outlined in Table 1.

The mismatch of parasitic parameters in the circuit is due to asymmetrical layout design (Graovac, 2009; Wang G. et al., 2014; Colmenares et al., 2015; Li et al., 2016; Haihong et al., 2017). This mismatch is the reason for the current imbalance which can be mitigated by realizing the symmetrical layout (Sadik et al., 2013). As mentioned earlier, the impact of L _s mismatch on current sharing is more prominent than that of L _d or L _g . Therefore, it is paramount to minimize discrepancy in L _s to reduce the current imbalance (La Mantia et al., 2017). Nevertheless, in many applications, due to layout constraints, it is extremely hard to achieve exactly symmetrical layout design. In such cases, a four-pin device that offers a kelvin connection can be adopted which provides a shorter path to the gate loop and bypass the L _s as shown in Figure 6B. Kelvin connection does not guarantee equal current distribution, yet it offers an opportunity to designers to achieve a better layout design, leading to improved current sharing.

This method can reduce the dynamic current imbalance and can provide a slight reduction in static current imbalance. For effective reduction of current imbalance, just realizing the symmetrical layout is not enough as it does not address the device mismatch. Generally, symmetrical layout design is a prerequisite for advanced current balancing methods. Besides, it does not offer increased switching speed, and energy losses cannot be minimized. Moreover, this method is difficult to adopt for more parallel-connected devices as the symmetrical layout is practically difficult to achieve for a higher number of devices.

Adjustment of gate or source resistor is a simple way to mitigate the current imbalance without adding any sensing or control circuit. One of the reasons for dynamic current imbalance is; a device with a lower V _th turns on earlier than the device with a higher V _th. There are two ways to reduce the effect of V _th mismatch using a gate resistor. First, the current imbalance can be suppressed by reducing the value of gate resistance if the same gate resistor is shared by the parallel-connected devices. Authors in Wang G. et al. (2014) achieved an effective reduction in current imbalance by reducing the gate resistance from 41 to 5.1 Ω at the cost of increased overshoot. The reason behind improved current sharing is; at a lower gate resistance, the switching speed increases and the effect of V _th mismatch become less significant. Another way is to add a suitable resistance only to the gate of the fast device with the lower V _th (Du et al., 2014). The fundamental principle behind adding the resistance is to delay the driving signal of the fast device (Du et al., 2014). Symmetrical layout is requisite for achieving promising results for both methods. Gate resistance adjustment can improve the dynamic current sharing and may offer a slight improvement in the current ratings. Nevertheless, it does not provide static current balancing since the V _th is the only parameter addressed in the strategy.

Employing additional source resistors in the parallel branches can suppress static current imbalance by reducing the R _DSon mismatch. As the source resistors can only reduce the R _DSon mismatch; therefore, no improvement in the dynamic current sharing can be attained and additional resistors cause extra power losses. Moreover, source resistors do not offer any reduction in voltage overshoot and gate oscillation (Zeng et al., 2020). Nonetheless, the cost, size and volume of gate and source resistance solutions are low and they can be employed for more than two devices.

This method aims to reduce the device mismatch using the transfer curve screening method to select the devices with similar characteristics to improve the current distribution. As mentioned earlier, the dynamic current balance is influenced by the threshold voltage (V _th) and transconductance (g _fs ). Researchers in Fuji Electric (2016) screened the devices based on only V _th, and limited reduction in current imbalance was achieved since the effect of g _fs was ignored (Lim et al., 2014; Wang G. et al., 2014; Kokosis et al., 2017). The scanning method adopted in Ke et al. (2018) takes into account both V _th and g _fs for screening the devices. The g _fs and V _th have the contrary effect on the current sharing as during turn-on transition, the device with larger g _fs carries a more current, and the device with larger V _th carries a less current as can be seen in Eq. 1 (Ke et al., 2018). ε = | x 1 − x 2 | ( x 1 − x 2 ) / 2 (5) μ ε = 1 n × ∑ k = 1 n ε k (6)

In this method, first of all, the transfer curves of all devices are drawn and a particular procedure, as demonstrated in Figure 10A, is used to select the curves. Subsequently, selected curves are discretized and corresponding points of curves are compared under the equal drain current to get the V _gs difference. Under the equal drain current, x ₁ and x ₂ are abscissa values of the two curves that are used to measure the relative difference ε by using Eq. 5. The average of the relative difference (μ _ε ), which represents the curve’s proximity, is then determined using Eq. 6, where n is the total number of sampling points and k is the serial number. The dominance of the transfer curve scanning method over the conventional counterpart is shown in Figure 10B, where among thirty tested devices, the devices with the lowest μ _ε (No. 20 and No. 27) accomplish better current sharing as compared to the devices with the smallest ΔV _th (No. 15 and No. 17).

This method provides effective dynamic current sharing along with improved current rating. It can be used for more than two devices. Achieving a symmetrical layout is essential to adopt this method, as the effect of circuit discrepancies is avoided in the results by accomplishing a symmetrical layout. Nevertheless, the gate oscillation, voltage overshoot and energy losses cannot be reduced. This method does not provide increased switching speed, and static current imbalance cannot be minimized since R _DSon is not considered. Furthermore, screening procedures are generally expensive and time-consuming (Graovac, 2009).

An Active Current Balancing (ACB) technique has been presented in Xue et al. (2014b), where an active gate driver is used to accomplish equal current sharing among parallel-connected SiC MOSFETs. The current imbalance occurs due to several reasons and it is hard to anticipate until the circuit is fabricated. ACB technique diminishes the current imbalance regardless of its cause (Xue et al., 2013). This method immediately detects a current imbalance, using a differential current transformer (DTC) employed at the drain of the parallel-connected devices as shown in Figure 11B. The current imbalance is suppressed by using the current balancing controller that actively adjusts the gate current with gate delay (Xue et al., 2014b). The system block diagram is illustrated in Figure 11A. There are three subsystem blocks: current sensing block (CSB), current balancing controller (CBC), and active gate control (AGC). The CSB detects the current using DTC whereas CBC takes the DCT’s current difference signal and extracts the imbalance during turn-on and turn-off events. CBC generates the appropriate signal for AGC to eliminate the imbalance. Finally, the AGC uses the instructions from the CBC to adjust the gate signals using a variable gate delay (VGD) circuit during turn-on and turn-off events. In this way, three blocks work together to reduce the current imbalance.

This method offers excellent dynamic current balancing and slightly improves the static current balance (Xue et al., 2014b). Moreover, this technique ensures small gate oscillation and low voltage overshoot. Although it does not improve the switching speed and no reduction in the energy losses was achieved. The complexity and cost of active current balancing are relatively higher due to additional sensing and control circuits. Besides, it does not ensure a small size and volume. In addition, the effective current balancing does not start from the first cycle; it takes more than ten cycles (Xue et al., 2014b). The high-bandwidth multi-channel current sensor requirement limits the adoption of this technique to two devices (Xue et al., 2014a). To address the current sensing issue, (Xue et al., 2014a) proposed a solution to measure the device’s current by using a PCB Rogowski coil current sensor. The design of the Rogowski coil is compact and planar along with high bandwidth, which allows accurate current measurement even with its dc component (Xue et al., 2014a). This method provides effective current sharing; however, the complexity of this method makes the integration tough.

Current distribution can be improved by incorporating additional coupled power-source inductors and drive-source resistors as shown in Figure 12. This is an innovative passive current balancing solution that applied one gate driver to parallel-connected MOSFETs without requiring any sensors or feedback system. The circuit diagram of parallel-connected SiC MOSFETs is shown in Figure 12A along with the parasitic parameters. The authors assumed the layout to be exactly symmetrical and ignored the effect of all layout stray inductances including the common source inductance (L _cm ) and the reduced diagram with compensating components as demonstrated in Figure 12B. The gate-source instance (L _k ) assists current balancing without causing voltage stress. The resistor (R _k ) enables voltage drop across the L _k . The loss impact of R _k in the gate loop is negligible as its size is extremely small compared with L _k . The power source inductor (L _s ) also assists the current balancing but increases the voltage stress as well. To avoid the voltage stress caused by the L _s, they are negatively coupled as clarified in Figure 12B. The equivalent circuit diagram is shown in Figure 12C where coupled inductors are substituted as mutual inductance (M _s ) and self-inductance (L _s ). With the implementation of these additional components the power-source inductance gets amplified from L _s to L _s + M _s and gets diminished from L _s to L _s − M _s during differential-mode and common-mode path, respectively, enabling improved current distribution along with reduced voltage overshoot, ringing, and EMI noise. By using this passive solution, the peak current difference of parallel-connected SiC MOSFETs is reduced from 15 to 3% without any additional voltage stress or switching loss. In-depth analysis and equations to determine the values of different parameters such as mutual inductance, self-inductance and resistance are presented in Mao et al. (2017a). Based on this technique, new passive current balancing solutions can also be explored by replacing the R _k with an inductor or with the combination of resistor and inductor.

This innovative approach reduces the static and dynamic current imbalance and improves the overall current rating (Mao et al., 2017a). In addition, this method limits the gate oscillations, ringing, EMI issues and it is a low-cost solution. The effect of layout mismatch is excluded by realizing the symmetrical design in this method. Although the integration is not easy, this method can be implemented for more than two devices.

Inspired by the common-mode choke’s success to mitigate common mode current in high frequency switching mode power supplies, authors in Zeng et al. (2020) employed a differential mode (DM) choke to suppress current imbalance among parallel-connected SiC MOSFETs, as the nature of imbalance current is a kind of differential mode. The implementation of DM choke for the current balancing between parallel-connected SiC MOSFETs is demonstrated in Figure 13A. The basic operation of the DM choke is illustrated in Figures 13B,C, which shows that there is no magnetic flux density (B _c ) in the case of balanced current (i _d1 = i _d2 ) and it is initiated by the imbalance current (i _d1 > i _d2 ) as shown in Figure 13C (Zeng et al., 2020). From the impedance perspective, imbalance current is shown in Eq. 7 where drain-source voltage is denoted by u _ds and Δi _d is the current difference. The impedances of parallel branches are represented by Z ₁ and Z ₂ . The difference of current flows through the DM choke windings when the impedance of parallel branches is not equal. The current imbalance gets reduced by the induced voltage (v _m ) shown in Eq. 8 where L _m is magnetic inductance. During imbalance current suppression, one winding of DM choke senses energy (P _in = v _m Δi _d ) and transforms electric energy into magnetic. Meanwhile, the other winding energy produces energy (P _in = −v _m Δi _d ) and transforms magnetic energy into electrical energy (Zeng et al., 2020). In this way, DM choke uses magnetic flux as a medium to transmit current between parallel branches. In ideal conditions, it enables current imbalance suppression without any energy loss. Detailed guidelines to design the DM choke are presented in Zeng et al. (2020). △ i d = u d s Z 1 − u d s Z 2 = u d s Z 1 − Z 2 Z 1 Z 2 (7) v m = L m ( d Δ i d / d t ) (8)

DM choke can effectively suppress both static and dynamic current imbalance even when different gate resistances are employed. In Zeng et al. (2020), parallel-connected SiC MOSFETs showed nearly identical current waveforms, including current rise and fall time and current peak value by employing DM choke. The DM choke improves the current ratings and reduces dv/dt which slightly diminishes the V _ds overshoot. Though the switching losses slightly increase, the turn-on and turn-off losses (E_on and E_off ) of parallel-connected devices are nearly the same. It is recommended to use the bifilar winding for the DM choke since it minimizes leakage inductance and equivalent parallel capacitance (EPC) (Zeng et al., 2020). This method can be extended to more than two devices. Mechanisms of interaction between DM choke and SiC MOSFETs need further research to explore cross-talk, short-circuit, etc. (Zeng et al., 2020). The cost and design effort of the DM choke method are lower than ACB because the former one does not require any complex control scheme and feedback. A comparison of the different methods is presented in Table 2.