The overall architecture of the neural stimulator is shown in Figure 4, which is mainly composed of three parts: main DAC module, synchronous charge detection module, and short-time pulse insertion circuit. The main DAC module contains two 6-bit current-mode DACs, which generate stimulation current ranging from 8 to 504 μA. S_charge and S_discharge are the switches to control cathodic stimulation and anodic stimulation respectively. The synchronous charge detection module includes a current splitter, an integrator circuit, and a compensation circuit. The current splitter shrinks the bidirectional stimulation current produced by the main DACs and the integrator circuit combined with logic control circuits are used to perform synchronous charge detection. In order to avoid process variation induced error and possible inaccuracy caused by scaling factor mismatch of the current splitter, the compensation circuit can regulate the input current of the current splitter. The short-time pulse insertion circuit is used to guarantee the residual charge remain in a safe range after multiple stimulation cycles. When the electrode voltage is out of the safe range (V _ref ± 25 mV) after the anodic stimulation pulse, a series of short-time pulses will be generated to draw the electrode voltage back to the reference voltage (V _ref ). To improve the safety of the neural stimulator with well charge balancing, residual charge detection circuit and short-time pulse insertion circuit are dedicatedly designed as these are the key blocks of the chip.

In synchronous charge detection module, the biphasic neural stimulation current are mirrored and shrunk with a certain ratio, and thus the total charge delivered to the electrode-tissue can be calculated and controlled by current integration with stimulation duration (Tan et al., 2011). Also, we use current splitter with very small current, in order to reduce the current consumption of these sub-circuits for charge detection. The current scaling ratio in the splitter circuit for current shrinking is designed as 1:10⁴, which cannot be completed directly through the traditional current mirror. Instead, this scaling factor can be implemented by the resistance current splitter in this work, and its circuit is shown in Figure 5. In the CMOS process technology, the on-chip resistor usually has large error and takes up large chip area in fabrication. The MOS transistor working in the deep linear region can be used in this design to replace the conventional N-well resistor or other on-chip resistance devices (Bult and Geelen, 1992; Linares-Barranco and Serrano-Gotarredona, 2003; Tan et al., 2011). Taking NMOS transistor as an example, the drain source impedance in deep linear region is r ds = ∂ V DS ∂ I D ≈ 1 μ n C ox W L ( V GS − V TH ) , (1) As shown in Eq. 1, r_ds is inversely proportional to the width and length ratio (W/L) of the transistor. Shown in Figure 5A, the working process of the MOS transistor resistor (M1-M4) based current splitter can be deduced as follows. Firstly, at circuit node N1, the ratio of the current allocated to M1 and M2 is I M 1 : I M 2 = r M 2 : r M 1 = ( N − 1 ) : 1. (2)

At circuit node N2, the current splitter can be expressed in resistance ratio: I M 4 : I M 1 + ( M 2 / / M 1 ) = r M 1 + ( M 2 / / M 1 ) : r M 4 , = N − 1 N + 1 N − 1 1 N − 1 + 1 : 1 N − 1 , = ( N − 1 ) : 1. (3)

It can be seen that at each shunt node, the current can be divided into two circuits with a ratio of (N-1). The initial current I₁ equals to I_{ref_ P}. The subsequent current is derived as follows. I 2 = I 1 N − 1 × N − 1 N = I 1 N , I m = I 1 N m − 2 ( N − 1 ) × N − 1 N = I 1 N m − 1 , I m + 1 = I 1 N m − 1 ( N − 1 ) × 1 N = I 1 N m ( N − 1 ) . (4)

Due to the inevitable process variation induced error, the NMOS current splitter and the PMOS current splitter cannot perfectly match the scaling factor. This mismatch error will affect the accuracy of the synchronous charge detection, which would require the charge balancing circuit to be further optimized. As such, in order to compensate for this mismatch, a compensation circuit at the current reference of the PMOS current splitter is used. The compensation circuit is controlled by an off-chip voltage with coarse and fine adjustment to realize feedback control according to the original matching offset, which improve the accuracy of the charge detection.

The schematic of the integrator circuit is shown in Figure 6A. It uses the shrinking current to synchronously detect the residual charge in the tissue (Fang et al., 2007). The circuit mainly includes an operational amplifier, six integral paths (C1-C6), a reset path (S_reset), and a comparator. The input of the integrator circuit is connected to the output of the current splitter. The six integrating paths correspond to the 6-bit switch of the DAC respectively. The switch (S_ reset) resets the initial output voltage (V _o ) to V _Reference . The output voltage of the integrator circuit with fixed capacitance is V o = 1 C int ∫ t 0 t i d t = 1 C int ∫ t 0 t ∑ n = 0 5 b i t n 2 n I r e f d t . (5)

C_int is the fixed integrating capacitance, I is the input current of the integrator, and bit _n is the control bit of the current mode DAC. The input current is controlled by bit _n , which takes different integration time to reach the same output voltage. Then, the output voltage of the integrating circuit using the adjustable capacitor array is V o = 1 C i n t ∫ t 0 t i d t = 1 ∑ n = 0 5 b i t n 2 n C r e f ∫ t 0 t ∑ n = 0 5 bit n 2 n I ref d t , ≈ 1 C r e f ∫ t 0 t   i r e f d t . (6) C_ref is the unit capacitance of the adjustable capacitor array. Because the input current and adjustable capacitor array are simultaneously controlled by bit _n , the integration time is consistent.

In the cathodic stimulation phase, the integrator circuit inputs a negative current and the output voltage (Vo) of the operational amplifier begins to rise. At this time, the charge stored on the capacitor is the synchronous charge injected into the neural tissue. When during the anodic stimulation phase, the input of the integrator circuit changes to the forwarding current, and Vo begins to decrease until the charge on the capacitor is discharged completely. Then, the comparator state is reversed and meanwhile the anode stimulation pulse is ended, which indicates that the synchronous charge detection process is over.

The comparator circuit needs to have high-speed and high-gain performances so as to make the switch S _{_charge} disconnect in time. In this design, three high-speed amplifiers are cascaded to form a comparator as shown in Figure 6B.

For the first-order operational amplifier, its frequency response A_v (s) is A v ( s ) = A v ( 0 ) s w c + 1 = A v ( 0 ) s τ c + 1 . (7)

A_v (0) is the DC gain of the open-loop comparator, τ_c = R_out ∗ C_L is the time constant, so its step response V_out (s) is V o u t ( s ) = A v ( s ) V i n ( s ) = A v ( 0 ) V i n s ( s τ c + 1 ) . (8)

Thus, the frequency response and step response of this comparator circuit are: A v 3 ( s ) = ( A v ( s ) ) 3 = ( A v ( 0 ) s τ c + 1 ) 3 , (9) V o u t 3 ( s ) = A v 3 ( s ) V i n ( s ) = ( A v ( 0 ) ) 3 V i n s ( s τ c + 1 ) 3 . (10)

So the inverse Laplace transform of Eq. 10 can be obtained as shown in. V o u t ( t ) = A v 3 V i n − A v 3 V in e ( − w c t ) − A v 3 V i n w c 2 t 2 e ( − w c t ) 2 − A v 3 V i n w c t e ( − w c t ) . (11)

According to Eq. 11, when the total gain of the comparator is 60 dB, the supply voltage is 1.8 V, and the input voltage of the comparator is 1.8 mV, the maximum transmission delay will depend on the dominant pole of the amplifier (F = 1/τ_c). The detail parameters used in our design after calculation are listed in Table 1.

The amount of imbalanced charge caused by transmission delay (t _p ) of the comparator is expressed in Eq. 12. Q = I p ∗ t p . (12) I _P is the anodic stimulation current. This imbalanced charge can also be offset by the previous compensation circuit.

Besides the transmission delay of the comparator, the offset voltage of the comparator also produce a time delay, which may account to t _p in Eq. 12, so the problem of offset voltage also needs to be solved. Therefore, auto-zero technology is used in the comparator design as shown in Figure 6C, which has a calibration phase and a comparison phase in operation (Brianti et al., 1998; Danchiv and Bodea, 2008). When the self-calibration system starts to work, switch S1 is open and switch S2 is closed. At this time, the offset voltage (Vos) is sampled and stored on capacitor C. When the comparison phase starts to operate, the switch S1 is closed and the switch S2 is open. The offset voltage stored on the capacitor C generates a correction current through the transconductance amplifier GM2 to compensate the offset voltage. As a result, the input offset voltage of the comparator will be removed. The whole compensation circuit adopts the fully differential mode with a large common-mode rejection ratio, to realize a stable compensation effect.

The neural stimulator starts to enter the pulse insertion stage when the cathodic and anodic stimulation pulses are both over. The block diagram of the short-time pulse insertion circuit with discrimination signal generation is shown in Figure 7A. The circuit consists of three comparators, three D flip-flops, two XOR gate circuits, and a data selector. First, the TRI signal triggers the D flip-flops and stores the comparison result of the electrode voltage and the reference voltage (1.65 V). Then, the comparison results of the remaining two comparators will be stored in Q2 and Q3 sequent with the CLK. If the comparison results recorded in Q2 and Q3 are equal, it indicates that at this moment the electrode voltage is outside the safe range (the safety window is V _ref ± 25mV). The data selector chooses the “1” port, and then XOR with the output of Q1 will trigger the compensation operation. If the stored voltages in Q2 and Q3 are inconsistent, it indicates that the electrode voltage is within the safe range. The data selector chooses the “0” port and turns off the compensation by XOR.

The short-time pulse insertion circuit is shown in Figure 7B, which is composed of the main DACs circuit and a series of transistor switches. The circuit generates the compensation signal S_signal through the short pulse insertion discrimination mechanism described above. The compensation polarity signal (Result) and control signal (DAC _{_P circuit} or DAC _{_N circuit} ) perform the short-time pulse insertion compensation, so the extra current will flow to the electrode-tissue interface for stimulation current compensation. When the electrode voltage returns to the safe range, the short-time pulse stops, and the compensation mechanism is turned off. As such, with the short-time pulse insertion circuit and synchronous charge detection module, the residual charge is minimized during neural stimulation.

The single-channel charge balanced neural stimulator is implemented in TSMC 180-nm CMOS process technology. The micrograph of the chip is shown in Figure 8. It includes a bandgap reference (BGR) circuit, two main DACs, two current splitters, two integrator circuits, a short-time pulse insertion circuit and logic control circuits. The total chip area is 900 μm × 840 μm.

The printed circuit board (PCB) for chip measurement includes a power module, a clock module, an implemented charge balanced neural stimulator chip, and a resistor and capacitor based tunable RC electrode-tissue model. The experiment setup for chip measurement is shown in Figure 9A. The two output port of the stimulator is connected to a load resistor (2 kΩ) on another electronic board (the white one in Figure 9A) and the reference voltage powered by a 1.65-V supply, respectively. The output current of the neural stimulator is set to 200 μA and the cathodic pulse width is set to 400 μs. Each stimulation cycle includes four stages: cathodic stimulation stage, interphase delay stage, anodic stimulation stage and short-time pulse compensation stage. The voltage waveforms captured by the oscilloscope is shown in Figure 9B. It can be seen that main function of the neural stimulator chip is validated. Figure 9C shows the waveforms when the stimulation parameters doubles (output current is set to 400 μA). It also can be seen that the pulse insertion circuit works during the interval time between each stimulation cycle. Because the insertion current of the short-time pulse circuit is small, the residual charge cannot be compensated quickly. At the end of pulse insertion, the electrode voltage returns to the reference voltage. Due to the limited resolution of ADCs in the oscilloscope for measuring, it is difficult to observe the tiny difference between the electrode voltage and reference voltage in a single cycle. But from the result showing multiple stimulation cycles, we can find that the electrode voltage keeps the value around the V _ref without drifting, which means the short-time pulse insertion circuit works properly.

The shaded portions in Figure 9B and Figure 9C represent the amount of charge injected and discharged to the electrode-tissue interface by the neural stimulator. The shaded area C1 and C2 represent the amount of charge injected in the cathodic stimulation stage, and A1 and A2 represent the amount of charge discharged in the anodic stimulation stage. The total charge of C1 is 80 nC (200 μA × 400 µs), and the charge of C2 is 160 nC (400 μA × 400 µs). The charge amount of A1 is 73.5 nC (105 μA × 700 µs) and A2 is 150 nC (200 μA × 750 µs). Ideally, the injected charge in cathodic stimulation phase and discharged charge in the anodic stimulation phase need to be completely same to ensure the safety of the neural stimulator. In practical, due to process-induced current mismatch and charge leakage, the residual charge has not been perfectly removed. We can see the shaded areas in Figure 9B and Figure 9C are almost matched and the residual charge before compensation is 6.5 and 10 nC, respectively, which indicates that the proposed synchronous charge detection module achieves decent charge balancing characteristics even without any compensation. If balanced positive current and negative current are generated using some matching technique, the final effect of the charge balancing will be better. Figure 10A–C show the captured voltage waveforms when the neural stimulator sets different stimulation pulse widths respectively. The clock frequency of the chip is 5 MHz and the chip can provide three optional pulse width (100, 200 and 400 µs), which meet the most application of neural stimulation.

Figure 11A shows the measurement setup using the RC electrode-tissue model on the same PCB. We connect the output of the stimulator to the on-chip RC load and use oscilloscope to observe the voltage waveforms on the load. The first-order electrode-tissue model (CH = 200 nF, RF = 100 MΩ, RS = 8 kΩ) is adopted. The reference voltage (1.65 V) is provided by an LDO module on the PCB. The cathodic stimulation pulse width is set to 400 μs and the cathodic stimulation current amplitude is set to 104 μA. The electrode waveform displayed on the oscilloscope is shown in Figure 11B. We can see the period of single-cycle neural stimulation is 1.6 ms, including cathodic stimulation pulse width of 400 µs, an interval time of 100 μs for interphase delay, anodic stimulation pulse width of 620 µs, and short pulse insertion time of 480 μs. In order to measure the amount of the residual charge, we take a cycle of stimulation waveform for calculation. As shown in Figure 11C, the shaded parts C3 and A3 correspond to the charge amounts of cathodic stimulation and anodic stimulation respectively. Due to the load used is a first-order electrode-tissue model, the electrode voltage during the stimulation phase is continuously rising and the injected charge is accumulated on the capacitor of the load. Therefore, the method for charge calculation is to count the product of capacitance and voltage change. The area of C3 is 20 nC (200 nF × 100 mV) and the area of A3 is 24 nC (200 nF × 120 mV). The residual charge in a single cycle is only 4 nC before any compensation.

When the stimulation current is set to 56 μA and the cathodic stimulation pulse width is set to 200 µs, and the compensation circuit is also operated by fine tuning of the control voltage at this time, we can see the anodic stimulation time is reduced, as shown in Figure 11D. Now, the single neural stimulation period is 800 µs, including cathodic stimulation time of 200 µs, interphase delay time of 50 µs, anodic stimulation time of 305 µs, and short-pulse insertion time of 245 μs. Similarly, the stimulation waveform of one cycle is taken for calculation. As shown in Figure 11E, the area of the shaded part C4 is 7 nC (200 nF × 35 mV), and the area of A4 is 7.8 nC (200 nF × 39 mV). Using the compensation circuit of the neural stimulator, the residual charge in a single cycle is reduced to only 0.8 nC. The curve representing the relation between the stimulation current and measured residual charge is show in Figure 12. The residual charge can be minimized ranging from 0.63 to 0.95 nC according to different stimulation amplitudes. Even for some fragile neural stimulation, the acceptable charge value is about 15 nC/phase (Huang et al., 1999; Yigit et al., 2019).

To provide a similar environment of neural tissue for experiment, the phosphate buffer solution (PBS) is further used for chip measurement as the PBS osmotic pressure and ion concentration are similar to human blood. As shown in Figure 13A, two concentric needle electrodes are used and connected to the neural stimulator. One stimulating electrode is inserted into the PBS solution, the other concentric needle electrode is connected to the reference voltage (1.65 V). A power supply provides 3.3-V voltage to the chip. The oscilloscope probe is hooked on the electrode to capture its voltage waveform. The stimulation current is 104 μA and the cathodic stimulation pulse width is 100 μs. The measured voltage waveforms are shown in Figure 13B. It can be seen that the whole stimulation period is 400 µs, including cathodic stimulation time of 100 µs, interphase delay time of 25 µs, anodic stimulation time of 155 µs, and short-pulse insertion time of 120 μs.

Different from the ideal first-order model presented in previous section, the characteristic impedance in PBS solution changes with the charge transfer process. Due to the inherent charge leakage of MOS switch and the possible charge leakage on other paths, the electrode voltage during the interphasic delay time does not remain to be a fix voltage value. It is a common practice to observe the voltage difference at the beginning and end of the stimulation cycle. The recognized safety range is ±50 mV (Ortmanns, 2007). The single cycle stimulation voltage waveform is shown in Figure 13C. At the end of the anodic pulse, we can observe that the residual voltage is 50 mV, which exceed the threshold of the short-time pulse circuit (±25 mV). Then the short-time pulse insertion is working to remove the residual charge in time. Comparing the beginning and end of the stimulation cycle, as shown as the dotted line in Figure 13C, the electrode voltage remains the same. As shown in Figure 13B, the electrode voltage can return to the reference voltage at the end of each stimulation cycle, which ensure the correct operation of the neural stimulator in the next cycle. Based on the test environment of PBS solution, the function and effectiveness of this design are verified, and ensure the safety of neural stimulator. Table 2 shows the comparison between this work and other articles. It can be seen from the table that our chip has advantage in smaller area and lower maximum residual charge based on synchronous charge detection and short-time pulse insertion technology.