Scientific charge-coupled devices (CCDs) are currently used in various applications that require very low noise performances. CCD readouts are often implemented via correlated double sampling (CDS) using switched-capacitor circuits or digital signal processing algorithms after analog-to-digital conversion. By adjusting the interval between the clamping and sample-and-hold stages, the CDS approach can flexibly filter low-frequency noise to enhance the signal-to-noise ratio (SNR) and reduce the noisy electrons. Although CDS cancels offset and flicker noise (a type of electronic noise with a frequency spectrum that follows the 1/f law with increasing frequency in sensor signal conditioning), it requires substantial circuitry for the conversion of the received photons to digital data (Dobrev and Neycheva, 2020). CDS integration with low-noise amplifiers and analog signal processing blocks in application-specific integrated circuits (ASICs) can also contribute to noise suppression. Different approaches have been developed to optimize CCD readouts, such as specialized ASICs for CCD controllers (Juramy et al., 2014; Bessia et al., 2023) and novel analysis methods to reduce the pixel readout times (Gach et al., 2003; Moroni et al., 2020). Additionally, the use of CCDs in scientific instrumentation like telescopes underscores the importance of selecting a detector with a low readout noise (RON) and designing efficient controllers for driving the CCDs (Howell, 2000). Advancements in gamma-ray astronomy have highlighted the significance of readout electronics design, especially for detectors like photomultiplier tubes and silicon photomultipliers, emphasizing the need for integrated microelectronic implementations and different signal readout strategies (Carminati and Fiorini, 2024).

In this context, digital-correlated double sampling (DCDS) is an innovative sensor readout approach that allows low-frequency noise and offers post-acquisition noise correction through intermittent sampling of an internal reference voltage. This feature allows real-time acquisition using digital techniques for high bandwidth (Paul et al., 2022; Bourgeois et al., 2017). The present study entails a DCDS implementation system that offers a cost-effective, low-power, and digital compact solution for CCD readout, which makes it a promising technique in astronomical observations and imaging systems.

The experimental setup was established in the clean room at Centro de Investigaciones Energéticas Medioambientales y Tecnológicas (CIEMAT), Madrid, Spain (Figure 1A) and is composed of a cryostat allowing a CCD readout. The detector used was a 200-µm-thick, fully depleted, back-illuminated device with an n-type silicon base provided by Hamamatsu Photonics Company. Then, a specific coating was developed that was sensitive in the range of 300–1,100 nm. The CCD was operated in the cooled state at 160 K after the experimental space was pumped to below 5×10^-5 mbar, and these conditions were controlled using a heater. The temperature controller ensures highly stable experimental conditions and maintains the setpoint such that the fluctuations are below 1%. A minimum duration of 1 h is always required to ensure that the contaminant does not freeze onto the detector; furthermore, the experiments are commenced at least 1 h later to ensure stable operating conditions. The signals detected by the CCD were connected to a preamplifier board located inside the cryostat using a Kapton cable that was maintained at a distance of 20 cm below the CCD. This board separates the biases, clocks, and video signals, and shielding layers were included to prevent electrical coupling. Finally, single-point grounding was used to minimize the noise and ground loops as well as ensure system stability, as noted by Casas et al. (2012).

The analog readout was based on the Monsoon architecture (Jiménez et al., 2016), which comprises a master control board in charge of the pixel acquisition node, an acquisition board that provides different CCD voltages, and a clock board that generates analog clocks for sequencing and shifting the burden within the CCD. Analog CCD characterization was performed by collecting image sequences with the CCD for different exposure times up to saturation. Two digital processing systems were used for the DCDS readout (Figure 1B). We also studied the impacts of oversampling using the 2.5 mega-samples per second (MSPS), 24-bit, AD7760 sigma–delta high-performance ADC board along with an Intel Altera Cyclone FPGA. The maximum internal clock frequency used is 20 MHz, and the decimation rate can be selected from the following values: 8, 16, 32, 64, 128, and 256. The pixel signals were obtained with the HSC-ADC-EVALCZ (Analog Devices, 2024), which is a high-speed converter evaluation platform that uses an FPGA-based buffer memory board to capture blocks of digital data from the AD9467; this 16-bit monolithic ADC is perfectly suitable for DCDS owing to its high conversion rate of up to 250 MHz. The memory board was connected to a personal computer via a USB port under VisualAnalog software to quickly evaluate the ADC capabilities for DCDS readout. The analog signal conditioning circuit designed with the ultralow differential amplifier ADL5562 was modified by removing the input impedance such that the input pixel signal could be increased to the full DR of the ADC. The data capture was synchronized to an external trigger that activated the three CCD readout systems for the same experimental conditions.

CDS reduces noise by taking two samples of the output signal, one before and one after the charge transfer, and subtracting them to cancel out the noise and offset error; it compares the reference and data levels of the CCD signals to reduce some of the noise components. The DCDS readout is usually composed of signal conditioning and oversampling processing (Figure 2). The number of ADC samples is related to the ADC frequency and system bandwidth. Furthermore, the pixels should not be sampled at the following intervals: 1) clamp period, which is the time required to restore the DC output (t is largely dependent on the system design and is commonly considered to be less than 10% of the pixel period); 2) settling period, which is the time required to stabilize the final value after a CCD charge transfer. Both these intervals are considered to be essential for ensuring accurate signal processing.

The simplest filter function is the averaging function that aims to replicate the ideal analog CDS function (Equation (1)) and requires at least two samples per pixel (i.e., reference and signal levels) to obtain the pixel value ( P ) . The value of P is computed as the ratio of the sum of all reference samples to the total number of reference samples minus the ratio of the sum of all signal samples to the total number of signal samples; here, r i refers to the reference samples, s i corresponds to the signal samples, and n represents the total number of reference and signal samples. Assuming that all noise sources are white, it can be shown that the root mean square (RMS) noise σ p of the pixels is proportional to the RMS noise of the samples σ sample , which is inversely proportional to the square root of the number of samples. S A D U = P = 1 n r ∑ i = 1 n r r i − 1 n s ∑ i = 1 n s s i ; σ p = σ sample n 2 . (1)

DCDS characterization was conducted using the optimal number of samples per pixel. Figure 3 shows the different readout capabilities for ADC selection. AD7760 (2.5 MSPS) achieves a maximum of 20 samples per pixel at 130 kpix/s, and AD9467 (250 MSPS) provides about 1,200 samples per pixel at 130 kpix/s. As the first step, the offline algorithms for CCD readout processing were developed and tested. Each pixel was evaluated by subtracting the reference voltage from the signal value. The absolute offset level indicates the signal measured from a region on the array where photoelectrons are not generated. For a CCD, the zero-electron level is determined by overscanning the detector’s horizontal register, where the average of the overscanned pixels represents the desired ADC offset level. For instance, the overscan pixels are virtual pixels generated by the electronics when the CCD is read, and this can be configured as extra rows of pixels to provide a measure of the electronic reference level. Hence, these pixels appear as strips along one or more sides of the CCD images, and the ADC offset is calculated as the signal from the overscan pixels that is subtracted from the signal value. The pixels must also be processed to remove samples associated with the clamp period. Figure 4 shows a part of this process by including up to 100 pixels as both the signal and overscan pixels. The clamp period was removed automatically during the preprocessing stage in the two DCDS systems.

According to Janesick et al. (1987), the PT method is a valuable tool for characterizing CCD imaging systems as it enables evaluation of the linearity, RON, dark current, SNR, and DR, among other parameters. The resulting pixel value S is determined using Equation (2) based on the average number of incident photons per pixel ( P ) , quantum efficiency ( η e ) , quantum yield gain ( η i ) , sensitivity of the sense node of the output amplifier ( S v ) , source follower gain ( A S F ) , CDS gain ( A CDS ) , and ADC gain ( A ADC ) . The detector input is quantified in units of incident photons, and the final output is obtained by converting each pixel signal to a digital number represented by S (in ADUs). Instead of measuring the individual transfer functions, all are combined into a single transfer function given by Equation (3). The noise is calculated from the standard deviation (SD) of the pixel values from the subarray after removing the offset value. Furthermore, the total noise, which includes RON, shot noise, and fixed-pattern noise (FPN), is the quadrature sum of the individual noise sources (Equation (4)). S = P ⋅ η e ⋅ η i ⋅ S v ⋅ A S F ⋅ A CDS ⋅ A CCD . (2) K = S A D U σ shot 2 ; η i = 1 . (3) σ total 2 = σ RON 2 + S K 2 + P N ⋅ S 2 . (4)

The PTC is used to determine the detector’s gain constant by converting the relative digital numbers from the detector to absolute units of electrons; this includes all data points spanning the DR from those with minimal light exposure to saturation. Typically, the exposure time is varied while maintaining the charge integration period and frame readout time constant in the PTC sequence. The noise is then calculated from the SD of the pixel values from the subarray after removing the offset value. Figure 5 shows the relationship between the CCD pixel noise and net signal, providing insights into the tradeoffs between noise and signal levels in CCD systems when using different ADCs. The CCD saturation levels were determined from the CCD noise for both DCDS systems.

Table 1 shows the K and FWC values obtained for the two readout systems compared with those for the analog Monsoon CDS. The FWCs obtained are in concordance with the values provided by the manufacturers (typically 150,000 e). The readout at 223 kpix/s was not possible from the AD7760 ADC owing to limitations. The K values obtained at 130 kpix/s for the analog CDS system, DCDS AD7760, and DCDS AD9467 were 0.46, 0.046, and 3.93 e/ADU, respectively.

Clapp et al. (2016) emphasized optimization of the weighted averaging approach and characterized the system performance using the unsettled samples within the pixel period. Considering this work as the reference, the PT method was applied along with different samples per pixel at 130 kpix/s. However, this produced an undesirable effect related to the signal level. Although the reference and signal regions are clearly differentiable from the clamp and settling periods at low signal levels, these intervals expand at high signal levels and invade the regions corresponding to the reference and signal samples. Consequently, the CCD noise increases for higher signal values.

RON was calculated from the SD of the pixels in the overscan region. Figure 6 presents performance comparisons of different readout techniques in terms of noise and gain, which are critical parameters for optimizing the CCD readout. The RON decreases as the number of samples per pixel increases, resulting in an RMS noise value of 6.26 e at 45 kpix/s, and gradually increases with readout speed. The RON obtained with the DCDS AD9467 is an improvement over that obtained with the analog Monsoon CDS system for a wide range of readout speeds. The RON obtained with the DCDS AD7760 is considerably higher at 130 kpix/s, with an out-of-scale value (285 e with K = 0.06 e/ADU) owing to the limitation of the maximum selected samples per pixel (6 samples) compared to the 700 samples per pixel selected for the AD9467. The number of samples per pixel is a crucial consideration for determining the performance at any given pixel rate, suggesting that careful control over the sampling can further influence the RON and overall system performance.

Figure 7 illustrates the net signal increases with exposure time for the two ADCs. Despite the differences in sampling rates, the net signal values in terms of electrons (red points) show similar ranges (up to 150,000 e) for both ADCs. Furthermore, saturation occurs after 25 s of exposure, demonstrating extremely good linearity. The SNR value of 19,853 (86 dB) obtained with AD9467 at 74 kpix/s was calculated as the ratio of the FWC to the RON of the detector system. The analog Monsoon CDS system provided an SNR value of 5,318 (75 dB) at the same frequency (the result was limited by the video board ADC).

The FPN is caused by the variations in charge collection from one pixel to another. Although the FPN may appear to be insignificant, with only a 1% pixel non-uniformity observed in CCD detectors, it significantly impacts the sensor’s DR and dramatically limits the signal-to-noise performance. Typically, the FPN is eliminated from images prior to data processing by subtracting consecutive images. This expands the region limited by the shot noise and enables gain calculation across the full DR of the system. The FPN is computed by subtracting the photon variance and RON from the overall noise, where σ Δ is the SD of the difference, as noted in Equation (5). The FPN is obtained as the pixelwise difference between two identical frames captured consecutively at the same exposure level; thus, an FPN value ( P N ) of 0.01 was obtained for the synchronized AD9467 board with the analog system in the CCD region of interest. However, P N could not be determined for the AD7760 platform owing to the lack of synchronization with the analog system. Thus, the value obtained with the analog system was used in the AD7760 PTC analysis. σ FPN 2 = σ T 2 + σ Δ 2 2 , σ FPN = P N ⋅ S . (5)

Previously, DCDS characterizations were conducted using offline DCDS Python algorithms involving analysis after data collection. In this section , we propose the implementation of real-time DCDS, where the data are instantaneously processed during acquisition. This approach enables immediate noise reduction and error correction, thereby enhancing the accuracy and quality of the results in real time. In this regard, the DCDS was implemented on a versatile and powerful platform that allows both high-performance processing and customized hardware acceleration. The Zynq-7000 FPGA system-on-a-chip (SoC) device from AMD Xilinx ZC706 (Xilinx, 2024) combines a dual-core ARM Cortex-A9 processing system with Xilinx programmable logic and is tightly integrated on a single device. Figure 8 illustrates the block diagram of the data acquisition and processing system as well as the electronic board used for the DCDS implementation.

The DCDS system is built around a customized hardware data manager IP core (Figure 9A). The algorithm offers great flexibility for weighting the ADC samples on each pedestal based on the input frequency of the DCDS signal. The operating mode of the IP core can be controlled with the clock ADC and three external signals, namely, the enable signal that initiates the CCD row, pixel size, and DCDS signals that provide the pixel rate information. The IP core module defines the ADC sample operating mode in the pixel region of interest; the samples captured in the reference region operate in the up-accumulator mode, while the samples captured in the signal region operate in the down-accumulator mode. The resulting values are then divided by the number of samples in the signal region. The operations are performed during the clamp period, and the results are output after 30 ADC clock cycles. At the end of the signal region, the final pixel value is transmitted via direct memory access (DMA) to the DDR memory. The DCDS post-implementation FPGA design and usage of FPGA resources are shown in Figure 9B. Less than 10% of the Zynq resources are used in the implementation, ensuring that the hardware design fits comfortably within the selected FPGA. The behaviors of the different IP cores comprising the DCDS readout were tested through simulations using the Vivado-integrated testbench. The final step was to provide a synthetic CCD video waveform for verification.

Figure 10A compares the different readout techniques and corresponding noise performances for the generated images. As examples, an image of the entire CCD under analog readout and a small CCD pixel size under DCDS readout are presented. Figure 10B shows a further comparison of the noise performances of a Python-based offline DCDS algorithm and the hardware-based DCDS implementation. To analyze the two methodologies, the same number of pixels from the overscan region were selected for each method, and the noise performances were evaluated by calculating the standard deviation of the selected pixels. The offline DCDS Python algorithm shows a higher noise characteristic ( σ = 3.5) with a wider distribution and a higher σ value compared to the DCDS hardware implementation ( σ = 2.3). Quantization issues are not a concern in this comparison as both methods use the same ADC. Assuming equal K values, the numbers of samples per pixel may vary between the methods, and this could be the key parameter for the observed differences in the results. Nevertheless, the outcomes demonstrate the absence of significant rounding errors and background electronic noise reduction of up to 37%.

Finally, according to the Monsoon report, the power dissipation for the analog Monsoon acquisition board with 12 channels states a is 25.1 W ± 5%, of which 12.5 W ± 5% of the total power corresponds to the common circuitry shared between all channels and is equal to the power needed per channel. Consequently, the estimated power consumption per channel was 13.6 W ± 5%. The power dissipation of the AD9467 DCDS readout system in the acquisition mode was 7.1 W ± 5%, which is much lower than that required for a single channel of the analog Monsoon board (47% power reduction).

Developing an effective DCDS algorithm requires a thorough understanding of both the signal characteristics and noise sources, which adds complexity to the readout system design. According to the dataset of the Teledyne E2V CCD used in this study (Photonics, 2024), it is possible to achieve a noise level of approximately 4 e at 50 kpix/s. The results obtained for the AD9467 DCDS and Monsoon analog readout systems at 74 kpix/s (7.1 e and 9.7 e, respectively) during characterization approach this value. The use of low-power operational transconductance amplifiers and power scaling capabilities allow further optimization of the performances of the signal acquisition amplifiers, which are mainly developed for analog CDS readouts (Coln and Mueck, 2020). In our research, the noise observed at low frequencies is attributable to an issue with the preamplifier’s bandwidth, which does not allow adequate responses at these frequency levels. This work experimentally demonstrates that the “weighted samples” method can significantly reduce the RON at low signal levels. Concurrently, research on the design of low-noise differential preamplifiers or even an ASIC preamplifier that can be mounted next to the detector also offers significant advantages for developing low-noise systems. DCDS readout systems have been shown to offer optimal strategies for selecting CDS timings, highlighting the linearity of the operations and their impacts on the final pixel values (Weatherill et al., 2019). However, many studies still aim to suppress flicker noise in the CCDs using special methods that require experimental validation (Stefanov, 2015).

Although CDS techniques have shown significant promise in reducing RON, challenges remain in balancing noise suppression with system complexity and power efficiency, particularly for high-density applications. Advancements in DCDS approaches have emerged as solutions to the limitations of traditional analog methods, particularly in large-scale systems. DCDS offers enhanced capabilities through real-time processing, greater flexibility, and improved precision, thereby overcoming many limitations of the traditional analog CDS implementations.

In this study, the challenge of optimizing the CCD readout was addressed by implementing advanced hardware and digital processing techniques. The goal was to validate innovative algorithms by analyzing and processing the digital samples obtained from CCD readings and explore the potential of digital processing for enhancing performance. To this end, a hardware system was developed for implementing the DCDS technique and was characterized across the full DR of the CCD. This system was built using a 16-bit ADC with a high sample rate of 250 MSPS, which provided significant improvements over a slower 24-bit ADC operating at 2.5 MSPS. As the number of samples per pixel increased, the RON decreased, which resulted in a minimal RMS noise level of 6.26 e at 45 kpix/s for the AD9467 system. These results show noise level improvements (9.7 e) achieved with analog processing at equivalent readout speeds. The PT method was crucial in assessing the performance of the DCDS readout. The experimental results indicate that the number of samples per pixel, their positions within the pixel readout cycle, and the pattern noise factor are essential parameters for achieving accurate K values. It is also noted that high signal levels can introduce difficulties, such as expanded transition regions and unreliable PT parameters, due to unwanted transition samples in the reference and/or signal regions.

Finally, the DCDS technique was designed around a customized hardware data manager IP core, offering great flexibility for weighting the ADC samples on each pixel pedestal. A real-time DCDS CCD readout system implemented using a Zynq FPGA demonstrated improved noise performance ( σ = 2.3) compared to offline processing ( σ = 3.5). Moreover, the power dissipation achieved with the AD9467 board (7.1 W) represents a substantial improvement over the 13.6 W observed with a single channel of the Monsoon analog acquisition board. The preliminary images obtained from online DCDS processing are promising and encourage further development of the customized digital system for comprehensive CCD readout. Future research efforts will thus be focused on developing adaptive algorithms to dynamically adjust the DCDS parameters in real time based on the observed noise characteristics and environmental conditions during CCD readout. The selection of a low-noise preamplifier and its optimization are also possible improvements to reduce the noise at low frequencies.