Accelerating Inference of Convolutional Neural Networks Using In-memory Computing - Dazzi, Martino; Sebastian, Abu; Benini, Luca; Eleftheriou, Evangelos (Frontiers in Computational Neuroscience, 2021)
In-memory computing (IMC) is a non-von Neumann paradigm that has recently established itself as a promising approach for energy-efficient, high throughput hardware for deep learning applications. One prominent application of IMC is that of performing matrix-vector multiplication in O(1) time complexity by mapping the synaptic weights of a neural-network layer to the devices of an IMC core. However, because of the significantly different pattern of execution compared toprevious computational paradigms, IMC requires a rethinking of the architectural design choicesmade when designing deep-learning hardware. In this work, we focus on application-specific,IMC hardware for inference of Convolution Neural Networks (CNNs), and provide methodologiesfor implementing the various architectural components of the IMC core. Specifically, we present methods for mapping synaptic weights and activations on the memory structures and give evidence of the various trade-offs therein, such as the one between on-chip memory requirements and execution latency. Lastly, we show how to employ these methods to implement a pipelineddataflow that offers throughput and latency beyond state-of-the-art for image classification tasks.