Ion-conducting devices were fabricated with a via structure and top and bottom electrodes, as shown in Figure 1. The active switching layer is the 300 Å Ge₂Se₃ layer adjacent to the bottom electrode.

Devices were fabricated on 100 mm p-type Si wafers with the bottom electrode of 250 Å Cr/500 Å W already deposited via chemical vapor deposition on the wafers (purchased from Encompass Distribution Services, Tracy, CA, USA). The bottom electrode was patterned, followed by 800 Å sputtered nitride (AJA International ATC Orion 5 UHV Magnetron sputtering system). A via etched through this nitride layer (Oxford Plasma Etcher) defines the device contact area. Via sizes for this work were 4 µm in diameter and there were at least 200 devices per wafer.

Wafers were pre-sputtered with Ar⁺ to remove any oxide species from the bottom electrode, followed by in situ sputter deposition of all of the remaining device layers and top tungsten electrode layer, using an AJA International ATC Orion 5 UHV Magnetron sputtering system. The target layer thicknesses were (from bottom to top): Ge₂Se₃ (300 Å)/SnSe (800 Å)/Ge₂Se₃ (150 Å)/Ag (500 Å)/Ge₂Se₃ (100 Å)/W (400 Å). The top three layers below the tungsten top electrode, corresponding to Ge₂Se₃/Ag/Ge₂Se₃, mix during fabrication, becoming one conductive layer. Final device etching was performed with a Veeco ME1001 ion-mill. The active switching layer is the 300 Å Ge₂Se₃ layer deposited adjacent to the bottom electrode. The SnSe layer provides Sn ions and isolates the Ge₂Se₃ layer from direct contact with the Ag layer.

Devices are initially in a high resistance state (megaohms to gigaohms range) following fabrication. The first programing operation applies a positive potential to the top electrode and forces Sn ions from the SnSe layer into the active Ge₂Se₃ layer (Campbell and Anderson, 2007; Devasia et al., 2010, 2012; Campbell, 2017). For the devices used in this work, in addition to Sn ions from the SnSe layer, Ag⁺ ions from the GeSeAg layer are also incorporated into the active layer during this first programing operation. A conductive pathway, likely comprised of multiple conductive channels (Banerjee and Chakravorty, 1999; La Barbera et al., 2015), forms due to incorporation of these ions into the active layer, resulting in a resistance drop. The resistance can be increased by application of a potential across the device that places the top electrode at a lower potential than the bottom electrode, thus forcing ions out of the conductive channel toward the top electrode. The resistance of a device is related at any time to the resultant conductivity of the active switching layer, which is in turn related to the amount of incorporated metal and organization of conductive channels within the active layer (Banerjee and Chakravorty, 1999; La Barbera et al., 2015). A description of SDC device operation and differences between the SDC device and other ion-conducting devices, such as the conductive bridged random access memory, is in Campbell (2017).

A DC (quasi-static) measurement of a typical memristor used in this work exhibits the current–voltage (IV) curve shown in Figure 3. The IV curve shows a device initially in a high resistance state, which is switched to a low resistance with the application of a positive potential and switched to a high resistance through application of a negative potential. To see this in Figure 3, the measurement starts at V = 0 and follows the direction of the arrows toward +0.5 V, and then sweeps backwards through V = 0 to −0.5 V and back to V = 0 V. The transition from a high to low resistance occurs when a threshold voltage is reached (marked with ‡ on IV curve). The transition from low to high resistance occurs at a reverse threshold voltage (marked with # on the IV curve). To prevent the device from being overheated after it switches to a low resistance, a compliance current of 100 µA is used to limit the current. Thus, when the current through the device reaches 100 µA as it switches from high to low resistance, it is clamped at that value. This appears as a flat line in the IV curve at current = 100 µA. This general “bowtie” IV response is characteristic of the SDC device.

The SDC memristor is classified as a “generic” memristor (Chua, 2015) as shown by the sinudoidal input frequency response IV curves for the memristor (Figure 4). As the frequency of the sinusoidal input is increased from 1 Hz toward 100 kHz, the IV curve shows positive and negative lobes that collapse into a straight line through the IV origin as the frequency is increased. This is one of the hallmark features of the generic memristor. It should be noted clearly that this does not indicate that the frequency response of the device is poor, as is often the misinterpretation when one sees this sinusoidal response. In fact, the device can respond quite well to short (nanoseconds) pulses, as is demonstrated in this and previous (Campbell, 2017) work.

All electrical measurements were performed at the wafer level using a Micromanipulator 6200 microprobe station and an Agilent B1500A Semiconductor Device Parameter Analyzer equipped with two 2-channel waveform generator/fast measurement units (WGFMUs). Each WGFMU was connected to an electrode on the memristor and used to generate the pre- and postsynaptic spikes. Device resistance was read immediately before and after each ΔT test by measuring the current during application of 20 mV DC potential across the memristor. A DC potential of 20 mV is low enough to avoid perturbing the state of the device. Figure 5 shows the STDP measurement set-up.

Each spike shape (Figure 2) function was separately created in software using the HP33250A arbitrary waveform generator drawing/creation program (BenchLink Arb) and exported as a waveform file. This function was then included in a C⁺⁺ program, along with the B1500 measurement commands for the STDP tests (described in Section “STDP Experiment”) for each given experiment. This program then controlled the B1500 for the duration of the STDP measurements and then it saved the data from the B1500 in the form of a csv file. Once created, the STDP testing program could be altered for each different pulse shape by simply creating a new spike shape and including that in the command code. Table 1 lists the measurement parameters for the pulse shape tested, the maximum ΔT achieved during the test, the time step size for the pulse (resolution between points on the spike), the amplitude of the pulse, and the number of devices tested with those conditions.

In STDP, the difference in time between the firing of pre- and postsynaptic neurons determines whether the “strength” of the connection between those neurons increases or decreases. Biologically, this is caused by a change in the ion concentration in the intracellular space between the neurons making it more or less conductive. It was shown (Bi and Poo, 2001) for a biological synapse that when the presynaptic spike arrives before the postsynaptic spike (ΔT > 0), the synapse exhibited increased synaptic weight (Δw > 0) and when the presynaptic spike arrives after the postsynaptic spike (ΔT < 0) that the synapse exhibited decreased synaptic weight (Δw < 0). If the two neurons fire close in time, they will have a larger influence on the change in the synapse strength.

To illustrate the STDP concept, Figure 6A shows an example of an action potential presynaptic spike function. Five postsynaptic spikes with the same function, just separated in time from the presynaptic spike (Figure 6A) by ΔT ∈ {−20, −10, 0, 10, 20}, are shown in Figure 6B. The corresponding difference signals (often referred to as resultant waveforms) between the presynaptic spike and each of the five postsynaptic spikes (plotted against ΔT and time) are shown in Figure 6C. Note how the shape, magnitudes, and polarity of the resultant signal changes as a function of ΔT. The difference signals are completely dependent on the shapes of the individual spikes. There are many potential pulse shapes that could be used in spiking neural networks that rely on STDP for learning [see examples in Zamarreño-Ramos et al. (2011)]. Four shapes inspired by these were used in the work described here (Figure 2).

In neuromorphic computing, the memristor acts as the synapse and is connected at the two electrode terminals to the pre- and postsynaptic neurons. The STDP experiment emulates nature by applying simple action potentials of the same pulse shape to the two electrodes of the memristor and varying the time between application of these action potentials, ΔT, rather than engineering specific pulse shapes in order to achieve desirable resistance programing. The resultant potential waveform across the memristor is the difference between the potentials applied separately to each electrode, resulting in a unique effective programing pulse shape for every ΔT. These unique programing pulses will change the resistance of the memristor to an extent that depends on the resultant pulse shape, allowing for a continuous (analog) range of programed resistances over a wide range of pulse widths.

In the STDP experiment performed in this work, a voltage pulse (“spike”) is applied to both electrodes of a memristor synapse at varying times, separated by ΔT. The resultant potential difference across the device is the actual programing potential. The STDP synaptic weight change, Δw%, is calculated from the initial (R₁) and final (R₂) resistance: (1)Δw%=(1R2−1R1)1Rmin⋅100 where R_min is the minimum resistance (or maximum conductance) measured for the device over all ΔT conditions and is used to normalize the maximum synaptic weight change to 1. The resistances R₁ and R₂ were measured before and after, respectively, a given ΔT test. Thus, a decrease in device resistance with application of the STDP pulses corresponds to +ΔT in this experiment, and a +Δw%. This means that a pulse is applied to the bottom electrode at a time +ΔT before a pulse is applied to the top electrode.

The four spike shapes used in this work (Figure 2) differed by the slope of the rising pulse edge, the slope between negative and positive peaks, and by adding flatness to the positive peak. The tested ΔT time ranges spanned from a maximum ΔT of 1 s to a minimum of 50 ns. Table 1 provides a summary of the ΔT timing used for each pulse shape. Responses on between 5 and 26 devices were measured for each pulse shape and timing test (as provided in Table 1). The results are reported at each ΔT measurement showing the average weight% change over the devices tested with the error bar corresponding to the SD of the data set. Error bars extend from ±½ SD. To clarify, if five devices were measured at every ΔT for pulse shape 1, then the average of the weight% change at a given ΔT (one weight% change at that ΔT for each device, corresponding to a total of five values) was calculated from the five values. The SD was calculated from those five values and used to generate the error bar at that ΔT point on the STDP graph.

Figure 7 shows an example of a resultant waveform produced by application of spikes with shape 1 applied to the top and bottom electrodes of a memristor, separated in time by ΔT = 250 ns. The full-width-half-maximum (FWHM) pulse width is defined on the positive-going portion of each waveform. ΔT is defined as the time between the peaks of the positive-going waveform on the top and bottom electrodes. Note that while there is a large positive peak in the center of the resultant waveform, it is followed by a negative peak, labeled trailing pulse, in Figure 7. For the ion-conducting memristors used in this work, the change in resistance is dependent on the electric field induced movement of metal ions within the active device layer. Thus, any portion of the resultant waveform with a potential higher than the minimum value needed move ions within the conductive pathway will change the resistance. Thus, in many ΔT cases, this trailing pulse can have a significant impact on the final device state and is, in fact, responsible for achieving an STDP response. An example of the resultant waveform for pulse shape 2 waveforms for the case of four ΔTs is given in the Supplementary Material, highlighting the regions that are above the switching voltage threshold for increasing or decreasing the resistance of the device.

The STDP test sequence used for each test type starts with ΔT = 0. ΔT is then incrementally increased and cycled between −ΔT and +ΔT (thus cycling between an increase and decrease in resistance) up to the maximum ΔT. Between programing steps, the resulting resistance is read. The next programing pulse is then applied to reprogram the memristor. To illustrate, in the Long test (Table 1), a portion of the test sequence from the starting point is: ΔT = 0, Read, ΔT = −10 ms, Read, ΔT = +10 ms, Read, ΔT = −20 ms, Read, ΔT = +20 ms, and so on, where the Read is the 20 mV DC measurement to determine device resistance. No attempt is made to reset the memristor to an “initial” state before the next programing sequence is begun. The change in resistance is the desired measurement, and when in operation in a network, the effect of the next pulse pair will be on a memristor that is already in an intermediate state.

In addition to the STDP tests, single-sided spike tests were performed where instead of applying the spike potentials to both electrodes, only the resultant potential difference waveform for a given ΔT was created, and then applied to the top electrode with the bottom electrode held at ground. The purpose of these tests was to verify the dependence of the resultant potential waveform on device programmability and to compare with the STDP test results at the ΔT corresponding to the tested resultant potential waveform. The single-sided tests included a “trailing edge cancelation” test in which the resultant potential amplitude on the last portion of the waveform was reduced (in 25% increments to 100% reduction/cancelation) in order to demonstrate a way to increase the Δw% by a simple pulse modification at a given ΔT.

The resultant pulse for most ΔT has a symmetric shape with a positive (negative) peak, a negative (positive) peak, or zone followed by another positive (negative) peak (see Figures 6C and 7). The memristor will experience a state change if any of the peaks in the resultant waveform exceeds the threshold voltage for writing or erasing. These multiple pulses in the resultant contribute ultimately to the overall STDP response, but it is possible to alter the overall STDP response curve by controlling the potential allowed beyond a threshold voltage. It thus might be desirable for the combined system (neurons and synapses) when doing learning and computation to not experience the later reprograming steps. If a pair of pulses could be found that did not produce multiple peaks, the system could have a more desirable global behavior. The effect of the trailing pulse, which is present in the spike pair resultant waveforms for the case of pulse shape 1 (Figure 7), was investigated by choosing one ΔT case and applying the resultant waveform to the top electrode, with varying amounts of suppression in the trailing pulse amplitude.

To investigate the effect of the resultant pulse shape on memristor programing, first it was verified that applying a signal with the same potential shape as the resultant waveform to the top electrode, while keeping the bottom electrode grounded would have the same overall effect as applying the pre- and postsynaptic pulses to the two terminals. The results of this test, Figure 11, show the expected similarity in shape and approximate Δw% between the normal (two-sided) STDP test with a spike pair and the resultant-only (single-sided) test.

To evaluate the effect of changing the trailing pulse amplitude, a fixed value of ΔT = ±250 ns was selected based on the data in Figure 11, since they both correspond to regions of low, but non-zero, Δw% so that the effect of altering the amplitude of the trailing pulse will be obvious. For pulse shape 1, the resultant waveform has values that exceed the device’s threshold switching value in both the positive and negative threshold directions (see Figure 7), resulting in changes of resistance both higher and lower values during the application of the pulse. The final portion of the pulse, the “trailing edge”, sets the total Δw%. The full effect of the trailing edge pulse can be seen in Figure 12 where a suppression of 100% (i.e., the last pulse segment is reduced to 0 V) results in a Δw% that is as high as in the maximum Δw% value during the STDP test (Figure 11; this occurs at about ΔT = 100 ns). Partial suppression of the trailing edge pulse results in incremental changes to the Δw%.

An estimate of the energy required to change the state of the memristor during STDP requires knowledge of the resistance of the device before, during, and at the conclusion of an applied pulse. Additionally, the resultant waveforms do not have simple pulse shapes. Therefore, an estimate of energy necessary to perform a spike induced change on a memristor is difficult for three major reasons: (1) the device resistance is changing during the application of the resultant waveform, both to higher and lower resistances; (2) the energy per pulse is different for every ΔT; and (3) the device resistance can be high initially and change between values of high resistance (lower energy) or it can be low and change between values of low resistance (higher energy).

To get a rough estimate of the energy per memristor, a range was calculated with the worst case assumption that the pulse was a rectangular pulse with an amplitude and pulse width (FWHM) as given in Table 1. It was next assumed that the device resistance was constant in a high resistance range of 100–500 kΩ, or a low resistance range of 1–10 kΩ, both ranges that are reasonable for the SDC device (Campbell, 2017). Using these values, the energy per memristor was estimated and is shown in Table 1. In all cases, these are most likely overestimates of the energy required. However, they do provide a quick look at the potential order of magnitude energy requirements.