A software defined aerospace payload testing platform based on AXI bus - Yin, Guodong; Zhao, Wenjie; Rao, Jianing; Zhang, Wanying; Kang, Jing; Xie, Yan; Ma, Miao; Du, Jiahao; Liu, Xiuxiu; Zhu, Yan; An, Junshe; Wang, Lianguo (Frontiers in Astronomy and Space Sciences, 2026)
This paper presents a software-defined hardware-in-the-loop (HIL) testing platform for aerospace payloads based on a single-chip FPGA, addressing key challenges in ground testing of complex aerospace payloads, including stringent real-time requirements, difficulty in multi-protocol interface adaptation, limited runtime configurability, and insufficient fault injection depth. The platform features an innovative unified System-on-Chip (SoC) architecture centered on the AXI (Advanced eXtensible Interface) bus. By standardizing heterogeneous communication protocol interfaces—such as those for aerospace telemetry, tracking, command, data transmission, and remote sensing—into configurable AXI peripheral modules, the design achieves protocol adaptation layer decoupling and efficient resource scheduling. Experimental results demonstrate that the platform achieves nanosecond-level (≤15 ns) ultra-low latency for real-time data interaction, meeting the stringent timing requirements of aerospace payload testing. The software-defined architecture enables runtime configuration of interface parameters without system restart or FPGA reprogramming, significantly enhancing test scenario flexibility. Furthermore, a white-box design approach exposes internal signals and status interfaces of the device under test, enabling fine-grained fault injection (including bit flips, timing anomalies, and message drops) into critical modules such as protocol stacks and data processing units, thereby overcoming the coverage limitations of traditional black-box testing. The platform has been deployed in multiple aerospace payload ground testing campaigns, where its nanosecond-level response latency and runtime configurability have significantly improved testing efficiency.